Fixed error that happens in HDL templates when 1-bit wide 'reserved' …

…field is defined at MSB position
esynr3z · Apr 26, 2023 · a30b267 · a30b267
1 parent 04e697c
commit a30b267
Show file tree

Hide file tree

Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/corsair/templates/regmap_verilog.j2 b/corsair/templates/regmap_verilog.j2
@@ -253,7 +253,7 @@ assign {{ sig_csr_rdata(reg) }}{{ range(bf.lsb - 1, tmp.last_bit) }} = {{ zeros(
         {% endif %}
         {% set tmp.last_bit = bf.msb + 1 %}
     {% endfor %}
-    {% if config['data_width'] - 1 > tmp.last_bit %}
+    {% if config['data_width'] > tmp.last_bit %}
 assign {{ sig_csr_rdata(reg) }}{{ range(config['data_width'] - 1, tmp.last_bit) }} = {{ zeros(config['data_width'] - tmp.last_bit) }};
     {% endif %}
 

diff --git a/corsair/templates/regmap_vhdl.j2 b/corsair/templates/regmap_vhdl.j2
@@ -362,7 +362,7 @@ begin
         {% endif %}
         {% set tmp.last_bit = bf.msb + 1 %}
     {% endfor %}
-    {% if config['data_width'] - 1 > tmp.last_bit %}
+    {% if config['data_width'] > tmp.last_bit %}
 {{ sig_csr_rdata(reg) }}{{ range(config['data_width'] - 1, tmp.last_bit) }} <= {{ zeros(config['data_width'] - tmp.last_bit) }};
     {% endif %}