ashistko/clz

CHANGELOG.md

@@ -0,0 +1,13 @@
+# Changelog
+
+All notable changes to this project will be documented in this file.
+
+## Version: 7.7.33
+
+### New
+ - MYCODE support and Ever suffixes
+ - Auto update patch version
+ - Co-authored-by: Tonjen <[email protected]>
+
+
+

llvm/CMakeLists.txt

@@ -33,7 +33,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR)
   set(LLVM_VERSION_MINOR 7)
 endif()
 if(NOT DEFINED LLVM_VERSION_PATCH)
-  set(LLVM_VERSION_PATCH 30)
+  set(LLVM_VERSION_PATCH 33)
 endif()
 if(NOT DEFINED LLVM_VERSION_SUFFIX)
   set(LLVM_VERSION_SUFFIX "")

llvm/lib/Target/TVM/TVMISD.def

@@ -50,3 +50,6 @@ HANDLE_NODETYPE(TUPLE)
 HANDLE_NODETYPE(TUPLEVAR)
 
 HANDLE_NODETYPE(UNTUPLE2)
+
+HANDLE_NODETYPE(UBITSIZE)
+

llvm/lib/Target/TVM/TVMISelLowering.cpp

@@ -121,6 +121,8 @@ TVMTargetLowering::TVMTargetLowering(const TargetMachine &TM,
 
   setTargetDAGCombine(ISD::ANY_EXTEND);
 
+  setBooleanContents(NegativeOneProduceNonZeroReceiveContent);
+
   // Expand these forms; we pattern-match the forms that we can handle in isel.
   for (auto Op : {ISD::BR_CC, ISD::SELECT_CC}) {
     setOperationAction(Op, MVT::i257, Expand);
@@ -129,6 +131,9 @@ TVMTargetLowering::TVMTargetLowering(const TargetMachine &TM,
     setOperationAction(Op, MVT::TVMBuilder, Expand);
     setOperationAction(Op, MVT::TVMCell, Expand);
   }
+
+  setOperationAction(ISD::CTTZ, MVT::i257, Custom);
+  setOperationAction(ISD::CTLZ, MVT::i257, Custom);
 }
 
 //===----------------------------------------------------------------------===//
@@ -438,6 +443,7 @@ void TVMTargetLowering::ReplaceNodeResults(SDNode *N,
   switch (N->getOpcode()) {
   default:
     llvm_unreachable("Do not know how to custom type legalize this operation!");
+    return;
   case ISD::GlobalAddress:
     Results.push_back(LowerGlobalAddress(SDValue(N, 0), DAG));
     return;
@@ -477,6 +483,69 @@ void TVMTargetLowering::LowerOperationWrapper(SDNode *N,
     Results.push_back(Res.getValue(I));
 }
 
+// TVMISD::IFELSE
+// Optimize compare with zero and branch.
+static SDValue performIFELSECombine(SDNode *N,
+                                    TargetLowering::DAGCombinerInfo &DCI,
+                                    SelectionDAG &DAG) {
+  SDValue Chain = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
+  SDValue ThenDest = N->getOperand(2);
+  SDValue ElseDest = N->getOperand(3);
+
+  if (N1.getOpcode() != ISD::SETCC)
+    return SDValue();
+  SDValue LHS = N1->getOperand(0);
+  SDValue RHS = N1->getOperand(1);
+  ISD::CondCode CC = cast<CondCodeSDNode>(N1->getOperand(2))->get();
+  if (CC != ISD::CondCode::SETNE && CC != ISD::CondCode::SETEQ)
+    return SDValue();
+  if (LHS.getValueType() != MVT::i257)
+    return SDValue();
+  if (isNullConstant(LHS))
+    std::swap(LHS, RHS);
+  if (!isNullConstant(RHS))
+    return SDValue();
+  if (CC == ISD::CondCode::SETEQ)
+    std::swap(ThenDest, ElseDest);
+  auto RV = DAG.getNode(TVMISD::IFELSE, SDLoc(N), MVT::Other, Chain, LHS, ThenDest, ElseDest);
+
+  // Do not add new nodes to DAG combiner worklist.
+  DCI.CombineTo(N, RV, false);
+
+  return SDValue();
+}
+
+// TVMISD::IFJMP
+// Optimize compare with zero and branch.
+static SDValue performIFJMPCombine(SDNode *N,
+                                   TargetLowering::DAGCombinerInfo &DCI,
+                                   SelectionDAG &DAG) {
+  SDValue Chain = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
+  SDValue Dest = N->getOperand(2);
+
+  if (N1.getOpcode() != ISD::SETCC)
+    return SDValue();
+  SDValue LHS = N1->getOperand(0);
+  SDValue RHS = N1->getOperand(1);
+  ISD::CondCode CC = cast<CondCodeSDNode>(N1->getOperand(2))->get();
+  if (CC != ISD::CondCode::SETNE)
+    return SDValue();
+  if (LHS.getValueType() != MVT::i257)
+    return SDValue();
+  if (isNullConstant(LHS))
+    std::swap(LHS, RHS);
+  if (!isNullConstant(RHS))
+    return SDValue();
+  auto RV = DAG.getNode(TVMISD::IFJMP, SDLoc(N), MVT::Other, Chain, LHS, Dest);
+
+  // Do not add new nodes to DAG combiner worklist.
+  DCI.CombineTo(N, RV, false);
+
+  return SDValue();
+}
+
 SDValue TVMTargetLowering::PerformDAGCombine(SDNode *N,
                                              DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;
@@ -486,6 +555,10 @@ SDValue TVMTargetLowering::PerformDAGCombine(SDNode *N,
     if (N->getOperand(0)->getValueType(0) == N->getValueType(0))
       return N->getOperand(0);
     break;
+  case TVMISD::IFELSE:
+    return performIFELSECombine(N, DCI, DAG);
+  case TVMISD::IFJMP:
+    return performIFJMPCombine(N, DCI, DAG);
   case ISD::TRUNCATE: {
     // TVM uses only one value type for all operations. This leads to folding
     // of all truncate nodes during legalization because there is no truncation
@@ -739,6 +812,24 @@ SDValue TVMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
   return SDValue();
 }
 
+SDValue TVMTargetLowering::LowerLeadingBits(SDValue Op,
+                                            SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  SDValue Val = Op.getOperand(0);
+  SDValue C257 = DAG.getConstant(256, DL, MVT::i257);
+  if (Op.getOpcode() == ISD::CTLZ) {
+    SDValue UBitSize = DAG.getNode(TVMISD::UBITSIZE, DL, MVT::i257, Val);
+    SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i257, C257, UBitSize);
+    return Sub;
+  } else if (Op.getOpcode() == ISD::CTTZ) {
+    // TODO not implemented yet
+    assert(false);
+    return Val;
+  } else
+    assert(false);
+}
+
+
 //===----------------------------------------------------------------------===//
 //                       TVM Inline Assembly Support
 //===----------------------------------------------------------------------===//

llvm/lib/Target/TVM/TVMISelLowering.h

@@ -69,6 +69,9 @@ class TVMTargetLowering : public TargetLowering {
 
   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 
+  // Provide custom lowering for leading zeros and leading ones calculation
+  SDValue LowerLeadingBits(SDValue Op, SelectionDAG &DAG) const;
+
   /// getTargetNodeName - This method returns the name of a target specific
   /// DAG node.
   const char *getTargetNodeName(unsigned Opcode) const override;
@@ -102,6 +105,7 @@ class TVMTargetLowering : public TargetLowering {
                                SmallVectorImpl<SDValue> &InVals) const override;
 
   // Custom lowering hooks.
+  SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;

llvm/lib/Target/TVM/TVMInstrInfo.td

@@ -60,6 +60,9 @@ def SDT_TVMConstU257     : SDTypeProfile<1, 1,
                            [SDTCisVT<0, i257>, SDTCisVT<1, i257>]>;
 def SDT_TVMGlobalAddressWrapper : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
 
+def SDT_TVMUbitsize      : SDTypeProfile<1, 1, [SDTCisVT<0, i257>,
+                                               SDTCisVT<1, i257>]>;
+
 //===----------------------------------------------------------------------===//
 // TVM specific node definitions
 //===----------------------------------------------------------------------===//
@@ -100,6 +103,8 @@ def TVMand       : SDNode<"TVMISD::AND", SDT_TVMAnd, []>;
 def TVMrshift    : SDNode<"TVMISD::RSHIFT", SDT_TVMRShift, []>;
 def TVMconst_u257 : SDNode<"TVMISD::CONST_U257", SDT_TVMConstU257, []>;
 
+def TVMUbitsize  : SDNode<"TVMISD::UBITSIZE", SDT_TVMUbitsize, []>;
+
 def TVMtuple
     : SDNode<"TVMISD::TUPLE", SDTypeProfile<0, -1, []>, [SDNPVariadic]>;
 def TVMtuplevar
@@ -365,6 +370,8 @@ def : Pat<(TVMand I257:$a, I257:$b), (AND I257:$a, I257:$b)>;
 def : Pat<(TVMrshift I257:$a, timm:$b), (SHRCONST I257:$a, imm:$b)>;
 def : Pat<(TVMrshift I257:$a, I257:$b), (SHR I257:$a, I257:$b)>;
 
+def : Pat<(TVMUbitsize I257:$a), (UBITSIZE I257:$a)>;
+
 // unsigned a / b = a DIV b
 // unsigned a % b = a MOD b
 class UintBinopPat<SDPatternOperator instr_op, Instruction instr> :