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Adding a generated Verilog (or other) source is currently not possible if the license check is being used.
There should be a way to skip the check for generated files or, alternatively, add the possibility to add an escape line to bypass the check for a given file.
The text was updated successfully, but these errors were encountered:
The license checker should then understand this information.
There should be a way to skip the check for generated files or, alternatively, add the possibility to add an escape line to bypass the check for a given file.
We should not have a way to bypass the license check.
Adding a generated Verilog (or other) source is currently not possible if the license check is being used.
There should be a way to skip the check for generated files or, alternatively, add the possibility to add an escape line to bypass the check for a given file.
The text was updated successfully, but these errors were encountered: