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quicklogic: Update new pin mapping CSV
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Signed-off-by: Rafal Kolucki <[email protected]>
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@koluckirafal
koluckirafal committed Nov 17, 2022
1 parent 6efdba0 commit 588e758
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Showing 2 changed files with 144 additions and 144 deletions.
4 changes: 2 additions & 2 deletions quicklogic/qlf_k4n8/boards.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ add_quicklogic_board(
DEVICE ${FAST_CORNER_DEVICE}
PINMAP_XML interface-mapping_24x24.xml
PACKAGE ${FAST_CORNER_DEVICE}
PINMAP qlf_k4n8-qlf_k4n8_umc22.csv
PINMAP qlf_k4n8-qlf_k4n8_umc22_24x24.csv
FABRIC_PACKAGE qlf_k4n8_umc22
)

Expand All @@ -17,6 +17,6 @@ add_quicklogic_board(
DEVICE ${SLOW_CORNER_DEVICE}
PINMAP_XML interface-mapping_24x24.xml
PACKAGE ${SLOW_CORNER_DEVICE}
PINMAP qlf_k4n8-qlf_k4n8_umc22.csv
PINMAP qlf_k4n8-qlf_k4n8_umc22_24x24.csv
FABRIC_PACKAGE qlf_k4n8_umc22
)
284 changes: 142 additions & 142 deletions quicklogic/qlf_k4n8/devices/umc22/qlf_k4n8-qlf_k4n8_umc22_24x24.csv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -563,15 +563,15 @@ Bottom,0,11,4,gfpga_pad_IO_F2A[980],F2P_MCLKO_1_OE,,,
Bottom,0,11,2,gfpga_pad_IO_A2F[978],P2F_MCLKO_2_IN,,,
Bottom,0,11,1,gfpga_pad_IO_F2A[977],F2P_MCLKO_2_OUT,,,
Bottom,0,11,0,gfpga_pad_IO_F2A[976],F2P_MCLKO_2_OE,,,
Bottom,0,12,0,gfpga_pad_IO_A2F[960],P2F_FCLKIO_HS,, CLK0 CLK3,
Bottom,0,13,7,gfpga_pad_IO_A2F[951],P2F_IXS8_SDI_HS,, CLK0,
Bottom,0,13,6,gfpga_pad_IO_A2F[950],P2F_IXS9_SDI_HS,, CLK0,
Bottom,0,13,5,gfpga_pad_IO_A2F[949],P2F_IXS10_SDI_HS,, CLK0,
Bottom,0,13,4,gfpga_pad_IO_A2F[948],P2F_IXS11_SDI_HS,, CLK0,
Bottom,0,13,3,gfpga_pad_IO_A2F[947],P2F_IXS12_SDI_HS,, CLK0,
Bottom,0,13,2,gfpga_pad_IO_A2F[946],P2F_IXS13_SDI_HS,, CLK0,
Bottom,0,13,1,gfpga_pad_IO_A2F[945],P2F_IXS14_SDI_HS,, CLK0,
Bottom,0,13,0,gfpga_pad_IO_A2F[944],P2F_IXS15_SDI_HS,, CLK0,
Bottom,0,12,0,gfpga_pad_IO_A2F[960],P2F_FCLKIO_HS,, CLK2 CLK3,
Bottom,0,13,7,gfpga_pad_IO_A2F[951],P2F_IXS8_SDI_HS,, CLK2,
Bottom,0,13,6,gfpga_pad_IO_A2F[950],P2F_IXS9_SDI_HS,, CLK2,
Bottom,0,13,5,gfpga_pad_IO_A2F[949],P2F_IXS10_SDI_HS,, CLK2,
Bottom,0,13,4,gfpga_pad_IO_A2F[948],P2F_IXS11_SDI_HS,, CLK2,
Bottom,0,13,3,gfpga_pad_IO_A2F[947],P2F_IXS12_SDI_HS,, CLK2,
Bottom,0,13,2,gfpga_pad_IO_A2F[946],P2F_IXS13_SDI_HS,, CLK2,
Bottom,0,13,1,gfpga_pad_IO_A2F[945],P2F_IXS14_SDI_HS,, CLK2,
Bottom,0,13,0,gfpga_pad_IO_A2F[944],P2F_IXS15_SDI_HS,, CLK2,
Bottom,0,14,4,gfpga_pad_IO_F2A[932],F2P_FCLKO_0_HS,, CLK3,
Bottom,0,14,3,gfpga_pad_IO_F2A[931],F2P_FCLKO_1_HS,, CLK3,
Bottom,0,14,2,gfpga_pad_IO_F2A[930],F2P_FCLKIO_HS,, CLK3,
Expand Down Expand Up @@ -745,98 +745,98 @@ Left,17,0,4,gfpga_pad_IO_A2F[1412],A2F_GPIO4_RD_ACK,,,
Left,17,0,3,gfpga_pad_IO_A2F[1411],RFU,,,
Left,17,0,1,gfpga_pad_IO_F2A[1409],F2A_ACM_FPGA_BCLK,,,
Left,17,0,0,gfpga_pad_IO_F2A[1408],F2A_ACM_APLL_BCLK,,,
Left,16,0,15,gfpga_pad_IO_F2A[1407],F2A_GPIO5_31,, CLK2 CLK3,
Left,16,0,14,gfpga_pad_IO_F2A[1406],F2A_GPIO5_30,, CLK2 CLK3,
Left,16,0,13,gfpga_pad_IO_F2A[1405],F2A_GPIO5_29,, CLK2 CLK3,
Left,16,0,12,gfpga_pad_IO_F2A[1404],F2A_GPIO5_28,, CLK2 CLK3,
Left,16,0,11,gfpga_pad_IO_A2F[1403],A2F_GPIO5_31,, CLK2 CLK3,
Left,16,0,10,gfpga_pad_IO_A2F[1402],A2F_GPIO5_30,, CLK2 CLK3,
Left,16,0,9,gfpga_pad_IO_A2F[1401],A2F_GPIO5_29,, CLK2 CLK3,
Left,16,0,8,gfpga_pad_IO_A2F[1400],A2F_GPIO5_28,, CLK2 CLK3,
Left,16,0,7,gfpga_pad_IO_A2F[1399],RFU,, CLK2 CLK3,
Left,16,0,6,gfpga_pad_IO_A2F[1398],RFU,, CLK2 CLK3,
Left,16,0,4,gfpga_pad_IO_A2F[1396],A2F_FIFOW_AEMPTY_HS,, CLK2 CLK3,
Left,16,0,2,gfpga_pad_IO_F2A[1394],F2A_FIFO_WE_HS,, CLK2 CLK3,
Left,16,0,1,gfpga_pad_IO_A2F[1393],A2F_FIFOW_FULL_HS,, CLK2 CLK3,
Left,16,0,0,gfpga_pad_IO_A2F[1392],A2F_FIFOW_EMPTY_HS,, CLK2 CLK3,
Left,15,0,15,gfpga_pad_IO_F2A[1391],F2A_GPIO5_27,, CLK2 CLK3,
Left,15,0,14,gfpga_pad_IO_F2A[1390],F2A_GPIO5_26,, CLK2 CLK3,
Left,15,0,13,gfpga_pad_IO_F2A[1389],F2A_GPIO5_25,, CLK2 CLK3,
Left,15,0,12,gfpga_pad_IO_F2A[1388],F2A_GPIO5_24,, CLK2 CLK3,
Left,15,0,11,gfpga_pad_IO_A2F[1387],A2F_GPIO5_27,, CLK2 CLK3,
Left,15,0,10,gfpga_pad_IO_A2F[1386],A2F_GPIO5_26,, CLK2 CLK3,
Left,15,0,9,gfpga_pad_IO_A2F[1385],A2F_GPIO5_25,, CLK2 CLK3,
Left,15,0,8,gfpga_pad_IO_A2F[1384],A2F_GPIO5_24,, CLK2 CLK3,
Left,15,0,7,gfpga_pad_IO_A2F[1383],A2F_FIFO_WD15_HS,, CLK2 CLK3,
Left,15,0,6,gfpga_pad_IO_A2F[1382],A2F_FIFO_WD14_HS,, CLK2 CLK3,
Left,15,0,5,gfpga_pad_IO_A2F[1381],A2F_FIFO_WD13_HS,, CLK2 CLK3,
Left,15,0,4,gfpga_pad_IO_A2F[1380],A2F_FIFO_WD12_HS,, CLK2 CLK3,
Left,15,0,3,gfpga_pad_IO_A2F[1379],A2F_FIFO_WD11_HS,, CLK2 CLK3,
Left,15,0,2,gfpga_pad_IO_A2F[1378],A2F_FIFO_WD10_HS,, CLK2 CLK3,
Left,15,0,1,gfpga_pad_IO_A2F[1377],A2F_FIFO_WD9_HS,, CLK2 CLK3,
Left,15,0,0,gfpga_pad_IO_A2F[1376],A2F_FIFO_WD8_HS,, CLK2 CLK3,
Left,14,0,15,gfpga_pad_IO_F2A[1375],F2A_GPIO5_23,, CLK2 CLK3,
Left,14,0,14,gfpga_pad_IO_F2A[1374],F2A_GPIO5_22,, CLK2 CLK3,
Left,14,0,13,gfpga_pad_IO_F2A[1373],F2A_GPIO5_21,, CLK2 CLK3,
Left,14,0,12,gfpga_pad_IO_F2A[1372],F2A_GPIO5_20,, CLK2 CLK3,
Left,14,0,11,gfpga_pad_IO_A2F[1371],A2F_GPIO5_23,, CLK2 CLK3,
Left,14,0,10,gfpga_pad_IO_A2F[1370],A2F_GPIO5_22,, CLK2 CLK3,
Left,14,0,9,gfpga_pad_IO_A2F[1369],A2F_GPIO5_21,, CLK2 CLK3,
Left,14,0,8,gfpga_pad_IO_A2F[1368],A2F_GPIO5_20,, CLK2 CLK3,
Left,14,0,7,gfpga_pad_IO_A2F[1367],A2F_FIFO_WD7_HS,, CLK2 CLK3,
Left,14,0,6,gfpga_pad_IO_A2F[1366],A2F_FIFO_WD6_HS,, CLK2 CLK3,
Left,14,0,5,gfpga_pad_IO_A2F[1365],A2F_FIFO_WD5_HS,, CLK2 CLK3,
Left,14,0,4,gfpga_pad_IO_A2F[1364],A2F_FIFO_WD4_HS,, CLK2 CLK3,
Left,14,0,3,gfpga_pad_IO_A2F[1363],A2F_FIFO_WD3_HS,, CLK2 CLK3,
Left,14,0,2,gfpga_pad_IO_A2F[1362],A2F_FIFO_WD2_HS,, CLK2 CLK3,
Left,14,0,1,gfpga_pad_IO_A2F[1361],A2F_FIFO_WD1_HS,, CLK2 CLK3,
Left,14,0,0,gfpga_pad_IO_A2F[1360],A2F_FIFO_WD0_HS,, CLK2 CLK3,
Left,13,0,15,gfpga_pad_IO_F2A[1359],F2A_GPIO5_19,, CLK2 CLK0,
Left,13,0,14,gfpga_pad_IO_F2A[1358],F2A_GPIO5_18,, CLK2 CLK0,
Left,13,0,13,gfpga_pad_IO_F2A[1357],F2A_GPIO5_17,, CLK2 CLK0,
Left,13,0,12,gfpga_pad_IO_F2A[1356],F2A_GPIO5_16,, CLK2 CLK0,
Left,13,0,11,gfpga_pad_IO_A2F[1355],A2F_GPIO5_19,, CLK2 CLK0,
Left,13,0,10,gfpga_pad_IO_A2F[1354],A2F_GPIO5_18,, CLK2 CLK0,
Left,13,0,9,gfpga_pad_IO_A2F[1353],A2F_GPIO5_17,, CLK2 CLK0,
Left,13,0,8,gfpga_pad_IO_A2F[1352],A2F_GPIO5_16,, CLK2 CLK0,
Left,13,0,7,gfpga_pad_IO_F2A[1351],F2A_FIFO_RD15_HS,, CLK2 CLK0,
Left,13,0,6,gfpga_pad_IO_F2A[1350],F2A_FIFO_RD14_HS,, CLK2 CLK0,
Left,13,0,5,gfpga_pad_IO_F2A[1349],F2A_FIFO_RD13_HS,, CLK2 CLK0,
Left,13,0,4,gfpga_pad_IO_F2A[1348],F2A_FIFO_RD12_HS,, CLK2 CLK0,
Left,13,0,3,gfpga_pad_IO_F2A[1347],F2A_FIFO_RD11_HS,, CLK2 CLK0,
Left,13,0,2,gfpga_pad_IO_F2A[1346],F2A_FIFO_RD10_HS,, CLK2 CLK0,
Left,13,0,1,gfpga_pad_IO_F2A[1345],F2A_FIFO_RD9_HS,, CLK2 CLK0,
Left,13,0,0,gfpga_pad_IO_F2A[1344],F2A_FIFO_RD8_HS,, CLK2 CLK0,
Left,12,0,15,gfpga_pad_IO_F2A[1343],F2A_GPIO5_15,, CLK2 CLK0,
Left,12,0,14,gfpga_pad_IO_F2A[1342],F2A_GPIO5_14,, CLK2 CLK0,
Left,12,0,13,gfpga_pad_IO_F2A[1341],F2A_GPIO5_13,, CLK2 CLK0,
Left,12,0,12,gfpga_pad_IO_F2A[1340],F2A_GPIO5_12,, CLK2 CLK0,
Left,12,0,11,gfpga_pad_IO_A2F[1339],A2F_GPIO5_15,, CLK2 CLK0,
Left,12,0,10,gfpga_pad_IO_A2F[1338],A2F_GPIO5_14,, CLK2 CLK0,
Left,12,0,9,gfpga_pad_IO_A2F[1337],A2F_GPIO5_13,, CLK2 CLK0,
Left,12,0,8,gfpga_pad_IO_A2F[1336],A2F_GPIO5_12,, CLK2 CLK0,
Left,12,0,7,gfpga_pad_IO_F2A[1335],F2A_FIFO_RD7_HS,, CLK2 CLK0,
Left,12,0,6,gfpga_pad_IO_F2A[1334],F2A_FIFO_RD6_HS,, CLK2 CLK0,
Left,12,0,5,gfpga_pad_IO_F2A[1333],F2A_FIFO_RD5_HS,, CLK2 CLK0,
Left,12,0,4,gfpga_pad_IO_F2A[1332],F2A_FIFO_RD4_HS,, CLK2 CLK0,
Left,12,0,3,gfpga_pad_IO_F2A[1331],F2A_FIFO_RD3_HS,, CLK2 CLK0,
Left,12,0,2,gfpga_pad_IO_F2A[1330],F2A_FIFO_RD2_HS,, CLK2 CLK0,
Left,12,0,1,gfpga_pad_IO_F2A[1329],F2A_FIFO_RD1_HS,, CLK2 CLK0,
Left,12,0,0,gfpga_pad_IO_F2A[1328],F2A_FIFO_RD0_HS,, CLK2 CLK0,
Left,11,0,15,gfpga_pad_IO_F2A[1327],F2A_GPIO5_11,, CLK2 CLK0,
Left,11,0,14,gfpga_pad_IO_F2A[1326],F2A_GPIO5_10,, CLK2 CLK0,
Left,11,0,13,gfpga_pad_IO_F2A[1325],F2A_GPIO5_9,, CLK2 CLK0,
Left,11,0,12,gfpga_pad_IO_F2A[1324],F2A_GPIO5_8,, CLK2 CLK0,
Left,11,0,11,gfpga_pad_IO_A2F[1323],A2F_GPIO5_11,, CLK2 CLK0,
Left,11,0,10,gfpga_pad_IO_A2F[1322],A2F_GPIO5_10,, CLK2 CLK0,
Left,11,0,9,gfpga_pad_IO_A2F[1321],A2F_GPIO5_9,, CLK2 CLK0,
Left,11,0,8,gfpga_pad_IO_A2F[1320],A2F_GPIO5_8,, CLK2 CLK0,
Left,11,0,7,gfpga_pad_IO_A2F[1319],RFU,, CLK2 CLK0,
Left,11,0,6,gfpga_pad_IO_A2F[1318],RFU,, CLK2 CLK0,
Left,11,0,5,gfpga_pad_IO_A2F[1317],A2F_FIFOR_AFULL_HS,, CLK2 CLK0,
Left,11,0,2,gfpga_pad_IO_F2A[1314],F2A_FIFO_RE_HS,, CLK2 CLK0,
Left,11,0,1,gfpga_pad_IO_A2F[1313],A2F_FIFOR_FULL_HS,, CLK2 CLK0,
Left,11,0,0,gfpga_pad_IO_A2F[1312],A2F_FIFOR_EMPTY_HS,, CLK2 CLK0,
Left,16,0,15,gfpga_pad_IO_F2A[1407],F2A_GPIO5_31,, CLK0 CLK3,
Left,16,0,14,gfpga_pad_IO_F2A[1406],F2A_GPIO5_30,, CLK0 CLK3,
Left,16,0,13,gfpga_pad_IO_F2A[1405],F2A_GPIO5_29,, CLK0 CLK3,
Left,16,0,12,gfpga_pad_IO_F2A[1404],F2A_GPIO5_28,, CLK0 CLK3,
Left,16,0,11,gfpga_pad_IO_A2F[1403],A2F_GPIO5_31,, CLK0 CLK3,
Left,16,0,10,gfpga_pad_IO_A2F[1402],A2F_GPIO5_30,, CLK0 CLK3,
Left,16,0,9,gfpga_pad_IO_A2F[1401],A2F_GPIO5_29,, CLK0 CLK3,
Left,16,0,8,gfpga_pad_IO_A2F[1400],A2F_GPIO5_28,, CLK0 CLK3,
Left,16,0,7,gfpga_pad_IO_A2F[1399],RFU,, CLK0 CLK3,
Left,16,0,6,gfpga_pad_IO_A2F[1398],RFU,, CLK0 CLK3,
Left,16,0,4,gfpga_pad_IO_A2F[1396],A2F_FIFOW_AEMPTY_HS,, CLK0 CLK3,
Left,16,0,2,gfpga_pad_IO_F2A[1394],F2A_FIFO_WE_HS,, CLK0 CLK3,
Left,16,0,1,gfpga_pad_IO_A2F[1393],A2F_FIFOW_FULL_HS,, CLK0 CLK3,
Left,16,0,0,gfpga_pad_IO_A2F[1392],A2F_FIFOW_EMPTY_HS,, CLK0 CLK3,
Left,15,0,15,gfpga_pad_IO_F2A[1391],F2A_GPIO5_27,, CLK0 CLK3,
Left,15,0,14,gfpga_pad_IO_F2A[1390],F2A_GPIO5_26,, CLK0 CLK3,
Left,15,0,13,gfpga_pad_IO_F2A[1389],F2A_GPIO5_25,, CLK0 CLK3,
Left,15,0,12,gfpga_pad_IO_F2A[1388],F2A_GPIO5_24,, CLK0 CLK3,
Left,15,0,11,gfpga_pad_IO_A2F[1387],A2F_GPIO5_27,, CLK0 CLK3,
Left,15,0,10,gfpga_pad_IO_A2F[1386],A2F_GPIO5_26,, CLK0 CLK3,
Left,15,0,9,gfpga_pad_IO_A2F[1385],A2F_GPIO5_25,, CLK0 CLK3,
Left,15,0,8,gfpga_pad_IO_A2F[1384],A2F_GPIO5_24,, CLK0 CLK3,
Left,15,0,7,gfpga_pad_IO_A2F[1383],A2F_FIFO_WD15_HS,, CLK0 CLK3,
Left,15,0,6,gfpga_pad_IO_A2F[1382],A2F_FIFO_WD14_HS,, CLK0 CLK3,
Left,15,0,5,gfpga_pad_IO_A2F[1381],A2F_FIFO_WD13_HS,, CLK0 CLK3,
Left,15,0,4,gfpga_pad_IO_A2F[1380],A2F_FIFO_WD12_HS,, CLK0 CLK3,
Left,15,0,3,gfpga_pad_IO_A2F[1379],A2F_FIFO_WD11_HS,, CLK0 CLK3,
Left,15,0,2,gfpga_pad_IO_A2F[1378],A2F_FIFO_WD10_HS,, CLK0 CLK3,
Left,15,0,1,gfpga_pad_IO_A2F[1377],A2F_FIFO_WD9_HS,, CLK0 CLK3,
Left,15,0,0,gfpga_pad_IO_A2F[1376],A2F_FIFO_WD8_HS,, CLK0 CLK3,
Left,14,0,15,gfpga_pad_IO_F2A[1375],F2A_GPIO5_23,, CLK0 CLK3,
Left,14,0,14,gfpga_pad_IO_F2A[1374],F2A_GPIO5_22,, CLK0 CLK3,
Left,14,0,13,gfpga_pad_IO_F2A[1373],F2A_GPIO5_21,, CLK0 CLK3,
Left,14,0,12,gfpga_pad_IO_F2A[1372],F2A_GPIO5_20,, CLK0 CLK3,
Left,14,0,11,gfpga_pad_IO_A2F[1371],A2F_GPIO5_23,, CLK0 CLK3,
Left,14,0,10,gfpga_pad_IO_A2F[1370],A2F_GPIO5_22,, CLK0 CLK3,
Left,14,0,9,gfpga_pad_IO_A2F[1369],A2F_GPIO5_21,, CLK0 CLK3,
Left,14,0,8,gfpga_pad_IO_A2F[1368],A2F_GPIO5_20,, CLK0 CLK3,
Left,14,0,7,gfpga_pad_IO_A2F[1367],A2F_FIFO_WD7_HS,, CLK0 CLK3,
Left,14,0,6,gfpga_pad_IO_A2F[1366],A2F_FIFO_WD6_HS,, CLK0 CLK3,
Left,14,0,5,gfpga_pad_IO_A2F[1365],A2F_FIFO_WD5_HS,, CLK0 CLK3,
Left,14,0,4,gfpga_pad_IO_A2F[1364],A2F_FIFO_WD4_HS,, CLK0 CLK3,
Left,14,0,3,gfpga_pad_IO_A2F[1363],A2F_FIFO_WD3_HS,, CLK0 CLK3,
Left,14,0,2,gfpga_pad_IO_A2F[1362],A2F_FIFO_WD2_HS,, CLK0 CLK3,
Left,14,0,1,gfpga_pad_IO_A2F[1361],A2F_FIFO_WD1_HS,, CLK0 CLK3,
Left,14,0,0,gfpga_pad_IO_A2F[1360],A2F_FIFO_WD0_HS,, CLK0 CLK3,
Left,13,0,15,gfpga_pad_IO_F2A[1359],F2A_GPIO5_19,, CLK0 CLK2,
Left,13,0,14,gfpga_pad_IO_F2A[1358],F2A_GPIO5_18,, CLK0 CLK2,
Left,13,0,13,gfpga_pad_IO_F2A[1357],F2A_GPIO5_17,, CLK0 CLK2,
Left,13,0,12,gfpga_pad_IO_F2A[1356],F2A_GPIO5_16,, CLK0 CLK2,
Left,13,0,11,gfpga_pad_IO_A2F[1355],A2F_GPIO5_19,, CLK0 CLK2,
Left,13,0,10,gfpga_pad_IO_A2F[1354],A2F_GPIO5_18,, CLK0 CLK2,
Left,13,0,9,gfpga_pad_IO_A2F[1353],A2F_GPIO5_17,, CLK0 CLK2,
Left,13,0,8,gfpga_pad_IO_A2F[1352],A2F_GPIO5_16,, CLK0 CLK2,
Left,13,0,7,gfpga_pad_IO_F2A[1351],F2A_FIFO_RD15_HS,, CLK0 CLK2,
Left,13,0,6,gfpga_pad_IO_F2A[1350],F2A_FIFO_RD14_HS,, CLK0 CLK2,
Left,13,0,5,gfpga_pad_IO_F2A[1349],F2A_FIFO_RD13_HS,, CLK0 CLK2,
Left,13,0,4,gfpga_pad_IO_F2A[1348],F2A_FIFO_RD12_HS,, CLK0 CLK2,
Left,13,0,3,gfpga_pad_IO_F2A[1347],F2A_FIFO_RD11_HS,, CLK0 CLK2,
Left,13,0,2,gfpga_pad_IO_F2A[1346],F2A_FIFO_RD10_HS,, CLK0 CLK2,
Left,13,0,1,gfpga_pad_IO_F2A[1345],F2A_FIFO_RD9_HS,, CLK0 CLK2,
Left,13,0,0,gfpga_pad_IO_F2A[1344],F2A_FIFO_RD8_HS,, CLK0 CLK2,
Left,12,0,15,gfpga_pad_IO_F2A[1343],F2A_GPIO5_15,, CLK0 CLK2,
Left,12,0,14,gfpga_pad_IO_F2A[1342],F2A_GPIO5_14,, CLK0 CLK2,
Left,12,0,13,gfpga_pad_IO_F2A[1341],F2A_GPIO5_13,, CLK0 CLK2,
Left,12,0,12,gfpga_pad_IO_F2A[1340],F2A_GPIO5_12,, CLK0 CLK2,
Left,12,0,11,gfpga_pad_IO_A2F[1339],A2F_GPIO5_15,, CLK0 CLK2,
Left,12,0,10,gfpga_pad_IO_A2F[1338],A2F_GPIO5_14,, CLK0 CLK2,
Left,12,0,9,gfpga_pad_IO_A2F[1337],A2F_GPIO5_13,, CLK0 CLK2,
Left,12,0,8,gfpga_pad_IO_A2F[1336],A2F_GPIO5_12,, CLK0 CLK2,
Left,12,0,7,gfpga_pad_IO_F2A[1335],F2A_FIFO_RD7_HS,, CLK0 CLK2,
Left,12,0,6,gfpga_pad_IO_F2A[1334],F2A_FIFO_RD6_HS,, CLK0 CLK2,
Left,12,0,5,gfpga_pad_IO_F2A[1333],F2A_FIFO_RD5_HS,, CLK0 CLK2,
Left,12,0,4,gfpga_pad_IO_F2A[1332],F2A_FIFO_RD4_HS,, CLK0 CLK2,
Left,12,0,3,gfpga_pad_IO_F2A[1331],F2A_FIFO_RD3_HS,, CLK0 CLK2,
Left,12,0,2,gfpga_pad_IO_F2A[1330],F2A_FIFO_RD2_HS,, CLK0 CLK2,
Left,12,0,1,gfpga_pad_IO_F2A[1329],F2A_FIFO_RD1_HS,, CLK0 CLK2,
Left,12,0,0,gfpga_pad_IO_F2A[1328],F2A_FIFO_RD0_HS,, CLK0 CLK2,
Left,11,0,15,gfpga_pad_IO_F2A[1327],F2A_GPIO5_11,, CLK0 CLK2,
Left,11,0,14,gfpga_pad_IO_F2A[1326],F2A_GPIO5_10,, CLK0 CLK2,
Left,11,0,13,gfpga_pad_IO_F2A[1325],F2A_GPIO5_9,, CLK0 CLK2,
Left,11,0,12,gfpga_pad_IO_F2A[1324],F2A_GPIO5_8,, CLK0 CLK2,
Left,11,0,11,gfpga_pad_IO_A2F[1323],A2F_GPIO5_11,, CLK0 CLK2,
Left,11,0,10,gfpga_pad_IO_A2F[1322],A2F_GPIO5_10,, CLK0 CLK2,
Left,11,0,9,gfpga_pad_IO_A2F[1321],A2F_GPIO5_9,, CLK0 CLK2,
Left,11,0,8,gfpga_pad_IO_A2F[1320],A2F_GPIO5_8,, CLK0 CLK2,
Left,11,0,7,gfpga_pad_IO_A2F[1319],RFU,, CLK0 CLK2,
Left,11,0,6,gfpga_pad_IO_A2F[1318],RFU,, CLK0 CLK2,
Left,11,0,5,gfpga_pad_IO_A2F[1317],A2F_FIFOR_AFULL_HS,, CLK0 CLK2,
Left,11,0,2,gfpga_pad_IO_F2A[1314],F2A_FIFO_RE_HS,, CLK0 CLK2,
Left,11,0,1,gfpga_pad_IO_A2F[1313],A2F_FIFOR_FULL_HS,, CLK0 CLK2,
Left,11,0,0,gfpga_pad_IO_A2F[1312],A2F_FIFOR_EMPTY_HS,, CLK0 CLK2,
Left,10,0,15,gfpga_pad_IO_F2A[1311],F2A_GPIO5_7,, CLK3,
Left,10,0,14,gfpga_pad_IO_F2A[1310],F2A_GPIO5_6,, CLK3,
Left,10,0,13,gfpga_pad_IO_F2A[1309],F2A_GPIO5_5,, CLK3,
Expand All @@ -853,22 +853,22 @@ Left,10,0,3,gfpga_pad_IO_A2F[1299],A2F_IXS11_SDO_HS,, CLK3,
Left,10,0,2,gfpga_pad_IO_A2F[1298],A2F_IXS10_SDO_HS,, CLK3,
Left,10,0,1,gfpga_pad_IO_A2F[1297],A2F_IXS9_SDO_HS,, CLK3,
Left,10,0,0,gfpga_pad_IO_A2F[1296],A2F_IXS8_SDO_HS,, CLK3,
Left,9,0,15,gfpga_pad_IO_F2A[1295],F2A_GPIO5_3,, CLK0,
Left,9,0,14,gfpga_pad_IO_F2A[1294],F2A_GPIO5_2,, CLK0,
Left,9,0,13,gfpga_pad_IO_F2A[1293],F2A_GPIO5_1,, CLK0,
Left,9,0,12,gfpga_pad_IO_F2A[1292],F2A_GPIO5_0,, CLK0,
Left,9,0,11,gfpga_pad_IO_A2F[1291],A2F_GPIO5_3,, CLK0,
Left,9,0,10,gfpga_pad_IO_A2F[1290],A2F_GPIO5_2,, CLK0,
Left,9,0,9,gfpga_pad_IO_A2F[1289],A2F_GPIO5_1,, CLK0,
Left,9,0,8,gfpga_pad_IO_A2F[1288],A2F_GPIO5_0,, CLK0,
Left,9,0,7,gfpga_pad_IO_F2A[1287],F2A_IXS15_SDI_HS,, CLK0,
Left,9,0,6,gfpga_pad_IO_F2A[1286],F2A_IXS14_SDI_HS,, CLK0,
Left,9,0,5,gfpga_pad_IO_F2A[1285],F2A_IXS13_SDI_HS,, CLK0,
Left,9,0,4,gfpga_pad_IO_F2A[1284],F2A_IXS12_SDI_HS,, CLK0,
Left,9,0,3,gfpga_pad_IO_F2A[1283],F2A_IXS11_SDI_HS,, CLK0,
Left,9,0,2,gfpga_pad_IO_F2A[1282],F2A_IXS10_SDI_HS,, CLK0,
Left,9,0,1,gfpga_pad_IO_F2A[1281],F2A_IXS9_SDI_HS,, CLK0,
Left,9,0,0,gfpga_pad_IO_F2A[1280],F2A_IXS8_SDI_HS,, CLK0,
Left,9,0,15,gfpga_pad_IO_F2A[1295],F2A_GPIO5_3,, CLK2,
Left,9,0,14,gfpga_pad_IO_F2A[1294],F2A_GPIO5_2,, CLK2,
Left,9,0,13,gfpga_pad_IO_F2A[1293],F2A_GPIO5_1,, CLK2,
Left,9,0,12,gfpga_pad_IO_F2A[1292],F2A_GPIO5_0,, CLK2,
Left,9,0,11,gfpga_pad_IO_A2F[1291],A2F_GPIO5_3,, CLK2,
Left,9,0,10,gfpga_pad_IO_A2F[1290],A2F_GPIO5_2,, CLK2,
Left,9,0,9,gfpga_pad_IO_A2F[1289],A2F_GPIO5_1,, CLK2,
Left,9,0,8,gfpga_pad_IO_A2F[1288],A2F_GPIO5_0,, CLK2,
Left,9,0,7,gfpga_pad_IO_F2A[1287],F2A_IXS15_SDI_HS,, CLK2,
Left,9,0,6,gfpga_pad_IO_F2A[1286],F2A_IXS14_SDI_HS,, CLK2,
Left,9,0,5,gfpga_pad_IO_F2A[1285],F2A_IXS13_SDI_HS,, CLK2,
Left,9,0,4,gfpga_pad_IO_F2A[1284],F2A_IXS12_SDI_HS,, CLK2,
Left,9,0,3,gfpga_pad_IO_F2A[1283],F2A_IXS11_SDI_HS,, CLK2,
Left,9,0,2,gfpga_pad_IO_F2A[1282],F2A_IXS10_SDI_HS,, CLK2,
Left,9,0,1,gfpga_pad_IO_F2A[1281],F2A_IXS9_SDI_HS,, CLK2,
Left,9,0,0,gfpga_pad_IO_F2A[1280],F2A_IXS8_SDI_HS,, CLK2,
Left,8,0,15,gfpga_pad_IO_F2A[1279],F2A_GPIO4_31,, CLK3,
Left,8,0,14,gfpga_pad_IO_F2A[1278],F2A_GPIO4_30,, CLK3,
Left,8,0,13,gfpga_pad_IO_F2A[1277],F2A_GPIO4_29,, CLK3,
Expand All @@ -883,31 +883,31 @@ Left,8,0,4,gfpga_pad_IO_F2A[1268],F2A_AC_IXS_RX_FCLK_HS,, CLK3,
Left,8,0,2,gfpga_pad_IO_A2F[1266],A2F_AC_FCLK_DIV_F_OUT_HS,, CLK3,
Left,8,0,1,gfpga_pad_IO_A2F[1265],A2F_AC_FCLK_FMT_F_OUT_HS,, CLK3,
Left,8,0,0,gfpga_pad_IO_A2F[1264],A2F_IXS_TX_FCLK_HS,, CLK3,
Left,7,0,15,gfpga_pad_IO_F2A[1263],F2A_GPIO4_27,, CLK0,
Left,7,0,14,gfpga_pad_IO_F2A[1262],F2A_GPIO4_26,, CLK0,
Left,7,0,13,gfpga_pad_IO_F2A[1261],F2A_GPIO4_25,, CLK0,
Left,7,0,12,gfpga_pad_IO_F2A[1260],F2A_GPIO4_24,, CLK0,
Left,7,0,11,gfpga_pad_IO_A2F[1259],A2F_GPIO4_27,, CLK0,
Left,7,0,10,gfpga_pad_IO_A2F[1258],A2F_GPIO4_26,, CLK0,
Left,7,0,9,gfpga_pad_IO_A2F[1257],A2F_GPIO4_25,, CLK0,
Left,7,0,8,gfpga_pad_IO_A2F[1256],A2F_GPIO4_24,, CLK0,
Left,7,0,7,gfpga_pad_IO_F2A[1255],RFU,, CLK0,
Left,7,0,6,gfpga_pad_IO_F2A[1254],RFU,, CLK0,
Left,7,0,4,gfpga_pad_IO_F2A[1252],F2A_AC_IXS_TX_FCLK_HS,, CLK0,
Left,7,0,3,gfpga_pad_IO_A2F[1251],A2F_AC_FCLK0B0_IN_HS,, CLK0,
Left,7,0,1,gfpga_pad_IO_A2F[1249],A2F_AC_FCLK_FMT_F_IN_HS,, CLK0,
Left,7,0,0,gfpga_pad_IO_A2F[1248],A2F_IXS_RX_FCLK_HS,, CLK0,
Left,6,0,15,gfpga_pad_IO_F2A[1247],F2A_GPIO4_23,, CLK2,
Left,6,0,14,gfpga_pad_IO_F2A[1246],F2A_GPIO4_22,, CLK2,
Left,6,0,13,gfpga_pad_IO_F2A[1245],F2A_GPIO4_21,, CLK2,
Left,6,0,12,gfpga_pad_IO_F2A[1244],F2A_GPIO4_20,, CLK2,
Left,6,0,11,gfpga_pad_IO_A2F[1243],A2F_GPIO4_23,, CLK2,
Left,6,0,10,gfpga_pad_IO_A2F[1242],A2F_GPIO4_22,, CLK2,
Left,6,0,9,gfpga_pad_IO_A2F[1241],A2F_GPIO4_21,, CLK2,
Left,6,0,8,gfpga_pad_IO_A2F[1240],A2F_GPIO4_20,, CLK2,
Left,6,0,3,gfpga_pad_IO_A2F[1235],"A2F_AC_FCLK0B1_IN_HS
(sync to ADLL_CLK)",, CLK2,
Left,6,0,0,gfpga_pad_IO_F2A[1232],RFU,, CLK2,
Left,7,0,15,gfpga_pad_IO_F2A[1263],F2A_GPIO4_27,, CLK2,
Left,7,0,14,gfpga_pad_IO_F2A[1262],F2A_GPIO4_26,, CLK2,
Left,7,0,13,gfpga_pad_IO_F2A[1261],F2A_GPIO4_25,, CLK2,
Left,7,0,12,gfpga_pad_IO_F2A[1260],F2A_GPIO4_24,, CLK2,
Left,7,0,11,gfpga_pad_IO_A2F[1259],A2F_GPIO4_27,, CLK2,
Left,7,0,10,gfpga_pad_IO_A2F[1258],A2F_GPIO4_26,, CLK2,
Left,7,0,9,gfpga_pad_IO_A2F[1257],A2F_GPIO4_25,, CLK2,
Left,7,0,8,gfpga_pad_IO_A2F[1256],A2F_GPIO4_24,, CLK2,
Left,7,0,7,gfpga_pad_IO_F2A[1255],RFU,, CLK2,
Left,7,0,6,gfpga_pad_IO_F2A[1254],RFU,, CLK2,
Left,7,0,4,gfpga_pad_IO_F2A[1252],F2A_AC_IXS_TX_FCLK_HS,, CLK2,
Left,7,0,3,gfpga_pad_IO_A2F[1251],A2F_AC_FCLK_0B0_IN_HS,, CLK2,
Left,7,0,1,gfpga_pad_IO_A2F[1249],A2F_AC_FCLK_FMT_F_IN_HS,, CLK2,
Left,7,0,0,gfpga_pad_IO_A2F[1248],A2F_IXS_RX_FCLK_HS,, CLK2,
Left,6,0,15,gfpga_pad_IO_F2A[1247],F2A_GPIO4_23,, CLK0,
Left,6,0,14,gfpga_pad_IO_F2A[1246],F2A_GPIO4_22,, CLK0,
Left,6,0,13,gfpga_pad_IO_F2A[1245],F2A_GPIO4_21,, CLK0,
Left,6,0,12,gfpga_pad_IO_F2A[1244],F2A_GPIO4_20,, CLK0,
Left,6,0,11,gfpga_pad_IO_A2F[1243],A2F_GPIO4_23,, CLK0,
Left,6,0,10,gfpga_pad_IO_A2F[1242],A2F_GPIO4_22,, CLK0,
Left,6,0,9,gfpga_pad_IO_A2F[1241],A2F_GPIO4_21,, CLK0,
Left,6,0,8,gfpga_pad_IO_A2F[1240],A2F_GPIO4_20,, CLK0,
Left,6,0,3,gfpga_pad_IO_A2F[1235],"A2F_AC_FCLK_0B1_IN_HS
(sync to ADLL_CLK)",, CLK0,
Left,6,0,0,gfpga_pad_IO_F2A[1232],RFU,, CLK0,
Left,5,0,15,gfpga_pad_IO_F2A[1231],F2A_GPIO4_19,,,
Left,5,0,14,gfpga_pad_IO_F2A[1230],F2A_GPIO4_18,,,
Left,5,0,13,gfpga_pad_IO_F2A[1229],F2A_GPIO4_17,,,
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