chore: Update MSR baselines for T2CL on Cascade Lake

This is to adjust baselines in response to commit a628a18 Author: Takahiro Itazuri <[email protected]> Date: Wed Aug 23 15:05:28 2023 +0000 fix(vmm): Pass through KVM-virtualizable bits on IA32_ARCH_CAPABILITIES Signed-off-by: Takahiro Itazuri <[email protected]>
firecracker-microvm · Sep 8, 2023 · 78ffb8a · 78ffb8a
1 parent 72a9091
commit 78ffb8a
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_4.14host_4.14guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_4.14host_4.14guest.csv
@@ -17,7 +17,7 @@ MSR_ADDR,VALUE
 0xcd,0x3
 0xce,0x80000000
 0xfe,0x508
-0x10a,0xaa0eb
+0x10a,0x40aa06b
 0x11e,0xbe702111
 0x140,0x0
 0x174,0x10

diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_4.14host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_4.14host_5.10guest.csv
@@ -17,7 +17,7 @@ MSR_ADDR,VALUE
 0xcd,0x3
 0xce,0x80000000
 0xfe,0x508
-0x10a,0xaa0eb
+0x10a,0x40aa06b
 0x11e,0xbe702111
 0x140,0x0
 0x174,0x10