chore: Update MSR baselines for T2CL on kernel 5.10

Now that our kernel 5.10 AMIs have the KVM patch to enable GDS_NO when the required microcode is installed on the host, updates MSR baselines. Signed-off-by: Patrick Roy <[email protected]>
firecracker-microvm · Sep 13, 2023 · dc9f432 · dc9f432
1 parent 3adf2aa
commit dc9f432
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Showing 4 changed files with 4 additions and 4 deletions.
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_4.14guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_4.14guest.csv
@@ -18,7 +18,7 @@ MSR_ADDR,VALUE
 0xcd,0x3
 0xce,0x80000000
 0xfe,0x508
-0x10a,0xaa0eb
+0x10a,0x40aa0eb
 0x11e,0xbe702111
 0x122,0x3
 0x140,0x0

diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv
@@ -18,7 +18,7 @@ MSR_ADDR,VALUE
 0xcd,0x3
 0xce,0x80000000
 0xfe,0x508
-0x10a,0xaa0eb
+0x10a,0x40aa0eb
 0x11e,0xbe702111
 0x122,0x3
 0x140,0x0

diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_4.14guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_4.14guest.csv
@@ -18,7 +18,7 @@ MSR_ADDR,VALUE
 0xcd,0x3
 0xce,0x80000000
 0xfe,0x508
-0x10a,0x2a0eb
+0x10a,0x402a0eb
 0x11e,0xbe702111
 0x122,0x3
 0x140,0x0

diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv
@@ -18,7 +18,7 @@ MSR_ADDR,VALUE
 0xcd,0x3
 0xce,0x80000000
 0xfe,0x508
-0x10a,0x2a0eb
+0x10a,0x402a0eb
 0x11e,0xbe702111
 0x122,0x3
 0x140,0x0