Rename 'ARM' interpreter 'InterpreterCPU'

src/dual/CMakeLists.txt

@@ -5,8 +5,8 @@ set(CMAKE_CXX_STANDARD 20)
 set(CMAKE_CXX_STANDARD_REQUIRED ON)
 
 set(SOURCES
-  src/arm/tablegen/tablegen.cpp
-  src/arm/arm.cpp
+  src/arm/interpreter/tablegen/tablegen.cpp
+  src/arm/interpreter/interpreter_cpu.cpp
   src/common/scheduler.cpp
   src/nds/arm7/apu.cpp
   src/nds/arm7/dma.cpp
@@ -50,14 +50,14 @@ set(SOURCES
 )
 
 set(HEADERS
-  src/arm/handlers/arithmetic.inl
-  src/arm/handlers/handler16.inl
-  src/arm/handlers/handler32.inl
-  src/arm/handlers/memory.inl
-  src/arm/tablegen/decoder.hpp
-  src/arm/tablegen/gen_arm.hpp
-  src/arm/tablegen/gen_thumb.hpp
-  src/arm/arm.hpp
+  src/arm/interpreter/handlers/arithmetic.inl
+  src/arm/interpreter/handlers/handler16.inl
+  src/arm/interpreter/handlers/handler32.inl
+  src/arm/interpreter/handlers/memory.inl
+  src/arm/interpreter/tablegen/decoder.hpp
+  src/arm/interpreter/tablegen/gen_arm.hpp
+  src/arm/interpreter/tablegen/gen_thumb.hpp
+  src/arm/interpreter/interpreter_cpu.hpp
   src/nds/video_unit/gpu/renderer/software/edge.hpp
   src/nds/video_unit/gpu/renderer/software/interpolator.hpp
 )

src/dual/src/arm/arm.cpp → src/dual/src/arm/interpreter/interpreter_cpu.cpp

@@ -1,9 +1,9 @@
 
-#include "arm.hpp"
+#include "interpreter_cpu.hpp"
 
 namespace dual::arm {
 
-  ARM::ARM(
+  InterpreterCPU::InterpreterCPU(
     Memory& memory,
     Scheduler& scheduler,
     CycleCounter& cycle_counter,
@@ -24,7 +24,7 @@ namespace dual::arm {
     }
   }
 
-  void ARM::Reset() {
+  void InterpreterCPU::Reset() {
     constexpr u32 nop = 0xE320F000;
 
     m_state = {};
@@ -36,7 +36,7 @@ namespace dual::arm {
     SetIRQFlag(false);
   }
 
-  void ARM::Run(int cycles) {
+  void InterpreterCPU::Run(int cycles) {
     if(GetWaitingForIRQ()) {
       m_cycle_counter.AddDeviceCycles((uint)cycles);
       return;
@@ -86,7 +86,7 @@ namespace dual::arm {
     }
   }
 
-  void ARM::SignalIRQ() {
+  void InterpreterCPU::SignalIRQ() {
     if(m_state.cpsr.mask_irq) {
       return;
     }
@@ -111,19 +111,19 @@ namespace dual::arm {
     ReloadPipeline32();
   }
 
-  void ARM::ReloadPipeline32() {
+  void InterpreterCPU::ReloadPipeline32() {
     m_opcode[0] = ReadWordCode(m_state.r15);
     m_opcode[1] = ReadWordCode(m_state.r15 + 4);
     m_state.r15 += 8;
   }
 
-  void ARM::ReloadPipeline16() {
+  void InterpreterCPU::ReloadPipeline16() {
     m_opcode[0] = ReadHalfCode(m_state.r15);
     m_opcode[1] = ReadHalfCode(m_state.r15 + 2);
     m_state.r15 += 4;
   }
 
-  void ARM::BuildConditionTable() {
+  void InterpreterCPU::BuildConditionTable() {
     for(int flags = 0; flags < 16; flags++) {
       bool n = flags & 8;
       bool z = flags & 4;
@@ -149,7 +149,7 @@ namespace dual::arm {
     }
   }
 
-  auto ARM::GetRegisterBankByMode(Mode mode) -> Bank {
+  auto InterpreterCPU::GetRegisterBankByMode(Mode mode) -> Bank {
     switch(mode) {
       case Mode::User:       return Bank::None;
       case Mode::System:     return Bank::None;
@@ -163,7 +163,7 @@ namespace dual::arm {
     ATOM_PANIC("invalid ARM CPU mode: 0x{:02X}", (uint)mode);
   }
 
-  void ARM::SwitchMode(Mode new_mode) {
+  void InterpreterCPU::SwitchMode(Mode new_mode) {
     auto old_bank = GetRegisterBankByMode((Mode)m_state.cpsr.mode);
     auto new_bank = GetRegisterBankByMode(new_mode);
 

src/dual/src/arm/arm.hpp → src/dual/src/arm/interpreter/interpreter_cpu.hpp

@@ -12,9 +12,9 @@
 
 namespace dual::arm {
 
-  class ARM final : public CPU {
+  class InterpreterCPU final : public CPU {
     public:
-      ARM(
+      InterpreterCPU(
         Memory& memory,
         Scheduler& scheduler,
         CycleCounter& cycle_counter,
@@ -109,8 +109,8 @@ namespace dual::arm {
 
       void Run(int cycles) override;
 
-      typedef void (ARM::*Handler16)(u16);
-      typedef void (ARM::*Handler32)(u32);
+      typedef void (InterpreterCPU::*Handler16)(u16);
+      typedef void (InterpreterCPU::*Handler32)(u32);
 
     private:
       enum class Condition {

src/dual/src/arm/interpreter/tablegen/gen_arm.hpp

@@ -0,0 +1,106 @@
+
+enum class MultiplyOpcode {
+  MUL   = 0b000,
+  MLA   = 0b001,
+  UMULL = 0b100,
+  UMLAL = 0b101,
+  SMULL = 0b110,
+  SMLAL = 0b111
+};
+
+enum class SignedMultiplyOpcode {
+  SMLAxy  = 0b1000,
+  SM__Wy  = 0b1001,
+  SMLALxy = 0b1010,
+  SMULxy  = 0b1011
+};
+
+template <u32 instruction>
+static constexpr auto GenerateHandlerARM() -> Handler32 {
+  const bool pre  = instruction & (1 << 24);
+  const bool add  = instruction & (1 << 23);
+  const bool wb   = instruction & (1 << 21);
+  const bool load = instruction & (1 << 20);
+
+  switch(GetARMInstructionType(instruction)) {
+    case ARMInstrType::HalfwordSignedTransfer: {
+      const bool immediate = instruction & (1 << 22);
+      const auto opcode = (instruction >> 5) & 3;
+
+      return &InterpreterCPU::ARM_HalfDoubleAndSignedTransfer<pre, add, immediate, wb, load, opcode>;
+    }
+    case ARMInstrType::Multiply: {
+      const bool set_flags = instruction & (1 << 20);
+
+      switch(static_cast<MultiplyOpcode>((instruction >> 21) & 0xF)) {
+        case MultiplyOpcode::MUL:   return &InterpreterCPU::ARM_Multiply<false, set_flags>;
+        case MultiplyOpcode::MLA:   return &InterpreterCPU::ARM_Multiply<true, set_flags>;
+        case MultiplyOpcode::UMULL: return &InterpreterCPU::ARM_MultiplyLong<false, false, set_flags>;
+        case MultiplyOpcode::UMLAL: return &InterpreterCPU::ARM_MultiplyLong<false, true, set_flags>;
+        case MultiplyOpcode::SMULL: return &InterpreterCPU::ARM_MultiplyLong<true, false, set_flags>;
+        case MultiplyOpcode::SMLAL: return &InterpreterCPU::ARM_MultiplyLong<true, true, set_flags>;
+      }
+
+      break;
+    }
+    case ARMInstrType::SingleDataSwap: {
+      const bool byte = instruction & (1 << 22);
+
+      return &InterpreterCPU::ARM_SingleDataSwap<byte>;
+    }
+    case ARMInstrType::StatusTransfer: {
+      const bool immediate = instruction & (1 << 25);
+      const bool use_spsr  = instruction & (1 << 22);
+      const bool to_status = instruction & (1 << 21);
+
+      return &InterpreterCPU::ARM_StatusTransfer<immediate, use_spsr, to_status>;
+    }
+    case ARMInstrType::BranchAndExchange:  return &InterpreterCPU::ARM_BranchAndExchangeMaybeLink<false>;
+    case ARMInstrType::CountLeadingZeros:  return &InterpreterCPU::ARM_CountLeadingZeros;
+    case ARMInstrType::BranchLinkExchange: return &InterpreterCPU::ARM_BranchAndExchangeMaybeLink<true>;
+    case ARMInstrType::SaturatingAddSubtract: {
+      const int opcode = (instruction >> 20) & 0xF;
+
+      return &InterpreterCPU::ARM_SaturatingAddSubtract<opcode>;
+    }
+    case ARMInstrType::SignedHalfwordMultiply: {
+      const bool x = instruction & (1 << 5);
+      const bool y = instruction & (1 << 6);
+
+      switch(static_cast<SignedMultiplyOpcode>((instruction >> 21) & 0xF)) {
+        case SignedMultiplyOpcode::SMLAxy:  return &InterpreterCPU::ARM_SignedHalfwordMultiply<true, x, y>;
+        case SignedMultiplyOpcode::SM__Wy:  return &InterpreterCPU::ARM_SignedWordHalfwordMultiply<!x, y>;
+        case SignedMultiplyOpcode::SMLALxy: return &InterpreterCPU::ARM_SignedHalfwordMultiplyLongAccumulate<x, y>;
+        case SignedMultiplyOpcode::SMULxy:  return &InterpreterCPU::ARM_SignedHalfwordMultiply<false, x, y>;
+      }
+
+      break;
+    }
+    case ARMInstrType::DataProcessing: {
+      const bool immediate = instruction & (1 << 25);
+      const bool set_flags = instruction & (1 << 20);
+      const auto opcode = static_cast<InterpreterCPU::ARMDataOp>((instruction >> 21) & 0xF);
+      const auto field4 = (instruction >> 4) & 0xF;
+
+      return &InterpreterCPU::ARM_DataProcessing<immediate, opcode, set_flags, field4>;
+    }
+    case ARMInstrType::SingleDataTransfer: {
+      const bool immediate = ~instruction & (1 << 25);
+      const bool byte = instruction & (1 << 22);
+
+      return &InterpreterCPU::ARM_SingleDataTransfer<immediate, pre, add, byte, wb, load>;
+    }
+    case ARMInstrType::BlockDataTransfer: {
+      const bool user_mode = instruction & (1 << 22);
+
+      return &InterpreterCPU::ARM_BlockDataTransfer<pre, add, user_mode, wb, load>;
+    }
+    case ARMInstrType::BranchAndLink: return &InterpreterCPU::ARM_BranchAndLink<(instruction >> 24) & 1>;
+    case ARMInstrType::CoprocessorRegisterXfer: return &InterpreterCPU::ARM_CoprocessorRegisterTransfer;
+    case ARMInstrType::SoftwareInterrupt: return &InterpreterCPU::ARM_SWI;
+    case ARMInstrType::BranchLinkExchangeImm: return &InterpreterCPU::ARM_BranchLinkExchangeImm;
+    default: break;
+  }
+
+  return &InterpreterCPU::ARM_Undefined;
+}

src/dual/src/arm/tablegen/gen_thumb.hpp → src/dual/src/arm/interpreter/tablegen/gen_thumb.hpp

@@ -6,113 +6,113 @@ static constexpr auto GenerateHandlerThumb() -> Handler16 {
       const auto opcode  = (instruction >> 11) & 3;
       const auto offset5 = (instruction >>  6) & 0x1F;
 
-      return &ARM::Thumb_MoveShiftedRegister<opcode, offset5>;
+      return &InterpreterCPU::Thumb_MoveShiftedRegister<opcode, offset5>;
     }
     case ThumbInstrType::AddSub: {
       const bool immediate = (instruction >> 10) & 1;
       const bool subtract  = (instruction >>  9) & 1;
       const auto field3 = (instruction >> 6) & 7;
 
-      return &ARM::Thumb_AddSub<immediate, subtract, field3>;
+      return &InterpreterCPU::Thumb_AddSub<immediate, subtract, field3>;
     }
     case ThumbInstrType::MoveCompareAddSubImm: {
       const auto opcode = (instruction >> 11) & 3;
       const auto rD = (instruction >> 8) & 7;
 
-      return &ARM::Thumb_MoveCompareAddSubImm<opcode, rD>;
+      return &InterpreterCPU::Thumb_MoveCompareAddSubImm<opcode, rD>;
     }
     case ThumbInstrType::ALU: {
-      const auto opcode = static_cast<ARM::ThumbDataOp>((instruction >> 6) & 0xF);
+      const auto opcode = static_cast<InterpreterCPU::ThumbDataOp>((instruction >> 6) & 0xF);
 
-      return &ARM::Thumb_ALU<opcode>;
+      return &InterpreterCPU::Thumb_ALU<opcode>;
     }
     case ThumbInstrType::HighRegisterOps: {
-      const auto opcode = static_cast<ARM::ThumbHighRegOp>((instruction >> 8) & 3);
+      const auto opcode = static_cast<InterpreterCPU::ThumbHighRegOp>((instruction >> 8) & 3);
       const bool high1 = (instruction >> 7) & 1;
       const bool high2 = (instruction >> 6) & 1;
 
-      return &ARM::Thumb_HighRegisterOps_BX<opcode, high1, high2>;
+      return &InterpreterCPU::Thumb_HighRegisterOps_BX<opcode, high1, high2>;
     }
     case ThumbInstrType::LoadStoreRelativePC: {
       const auto rD = (instruction >> 8) & 7;
 
-      return &ARM::Thumb_LoadStoreRelativePC<rD>;
+      return &InterpreterCPU::Thumb_LoadStoreRelativePC<rD>;
     }
     case ThumbInstrType::LoadStoreOffsetReg: {
       const auto opcode = (instruction >> 10) & 3;
       const auto rO = (instruction >>  6) & 7;
 
-      return &ARM::Thumb_LoadStoreOffsetReg<opcode, rO>;
+      return &InterpreterCPU::Thumb_LoadStoreOffsetReg<opcode, rO>;
     }
     case ThumbInstrType::LoadStoreSigned: {
       const auto opcode = (instruction >> 10) & 3;
       const auto rO = (instruction >>  6) & 7;
 
-      return &ARM::Thumb_LoadStoreSigned<opcode, rO>;
+      return &InterpreterCPU::Thumb_LoadStoreSigned<opcode, rO>;
     }
     case ThumbInstrType::LoadStoreOffsetImm: {
       const auto opcode  = (instruction >> 11) & 3;
       const auto offset5 = (instruction >>  6) & 0x1F;
 
-      return &ARM::Thumb_LoadStoreOffsetImm<opcode, offset5>;
+      return &InterpreterCPU::Thumb_LoadStoreOffsetImm<opcode, offset5>;
     }
     case ThumbInstrType::LoadStoreHword: {
       const bool load = (instruction >> 11) & 1;
       const auto offset5 = (instruction >> 6) & 0x1F;
 
-      return &ARM::Thumb_LoadStoreHword<load, offset5>;
+      return &InterpreterCPU::Thumb_LoadStoreHword<load, offset5>;
     }
     case ThumbInstrType::LoadStoreRelativeSP: {
       const bool load = (instruction >> 11) & 1;
       const auto rD = (instruction >> 8) & 7;
 
-      return &ARM::Thumb_LoadStoreRelativeToSP<load, rD>;
+      return &InterpreterCPU::Thumb_LoadStoreRelativeToSP<load, rD>;
     }
     case ThumbInstrType::LoadAddress: {
       const bool use_r13 = (instruction >> 11) & 1;
       const auto rD = (instruction >> 8) & 7;
 
-      return &ARM::Thumb_LoadAddress<use_r13, rD>;
+      return &InterpreterCPU::Thumb_LoadAddress<use_r13, rD>;
     }
     case ThumbInstrType::AddOffsetToSP: {
       const bool subtract = (instruction >> 7) & 1;
 
-      return &ARM::Thumb_AddOffsetToSP<subtract>;
+      return &InterpreterCPU::Thumb_AddOffsetToSP<subtract>;
     }
     case ThumbInstrType::PushPop: {
       const bool load  = (instruction >> 11) & 1;
       const bool pc_lr = (instruction >>  8) & 1;
 
-      return &ARM::Thumb_PushPop<load, pc_lr>;
+      return &InterpreterCPU::Thumb_PushPop<load, pc_lr>;
     }
     case ThumbInstrType::LoadStoreMultiple: {
       const bool load = (instruction >> 11) & 1;
       const auto rB = (instruction >> 8) & 7;
 
-      return &ARM::Thumb_LoadStoreMultiple<load, rB>;
+      return &InterpreterCPU::Thumb_LoadStoreMultiple<load, rB>;
     }
     case ThumbInstrType::ConditionalBranch: {
       const auto condition = (instruction >> 8) & 0xF;
 
-      return &ARM::Thumb_ConditionalBranch<condition>;
+      return &InterpreterCPU::Thumb_ConditionalBranch<condition>;
     }
     case ThumbInstrType::SoftwareInterrupt: {
-      return &ARM::Thumb_SWI;
+      return &InterpreterCPU::Thumb_SWI;
     }
     case ThumbInstrType::UnconditionalBranch: {
-      return &ARM::Thumb_UnconditionalBranch;
+      return &InterpreterCPU::Thumb_UnconditionalBranch;
     }
     case ThumbInstrType::LongBranchLinkPrefix: {
-      return &ARM::Thumb_LongBranchLinkPrefix;
+      return &InterpreterCPU::Thumb_LongBranchLinkPrefix;
     }
     case ThumbInstrType::LongBranchLinkSuffix: {
-      return &ARM::Thumb_LongBranchLinkSuffix<false>;
+      return &InterpreterCPU::Thumb_LongBranchLinkSuffix<false>;
     }
     case ThumbInstrType::LongBranchLinkExchangeSuffix: {
-      return &ARM::Thumb_LongBranchLinkSuffix<true>;
+      return &InterpreterCPU::Thumb_LongBranchLinkSuffix<true>;
     }
     default: break;
   }
 
-  return &ARM::Thumb_Unimplemented;
+  return &InterpreterCPU::Thumb_Unimplemented;
 }