Make nasm the new default intel flavor

flysand7 · Oct 5, 2024 · eb54c8a · eb54c8a
1 parent 4860d91
commit eb54c8a
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Showing 4 changed files with 19 additions and 154 deletions.
diff --git a/src/disasm-cli/main.odin b/src/disasm-cli/main.odin
@@ -22,7 +22,6 @@ Options:
     Specify the assembly output flavor. Options:
     * intel (default) - Print x86 disasm's intel-style assembly.
     * att - Print AT&T style assembly, like in gas.
-    * nasm - Print assembly that tries to match ndisasm output as much as possible.
 -format:<format>
     Specify the format of the input file. Options:
     * auto (default) - Auto-detect a format (the default).
@@ -249,7 +248,9 @@ main :: proc() {
             switch str {
             case "intel": print_flavor = .Intel
             case "att": print_flavor = .ATT
-            case "nasm": print_flavor = .Nasm
+            case:
+                fmt.eprintfln("Unknown syntax flavor: %s", str)
+                os.exit(2)
             }
         } else {
             fmt.eprintfln("The -flavor option expects a string")

diff --git a/src/disasm/print.odin b/src/disasm/print.odin
@@ -5,14 +5,12 @@ import "core:io"
 Syntax_Variant :: enum {
     Intel,
     ATT,
-    Nasm,
 }
 
 print_one :: proc(w: io.Writer, addr: u64, inst: Instruction, syntax: Syntax_Variant) -> io.Error {
     switch syntax {
         case .Intel: return print_intel(w, addr, inst)
         case .ATT: return print_att(w, addr, inst)
-        case .Nasm: return print_nasm(w, addr, inst)
         case: panic("Unexpected syntax variant supplied.")
     }
     return .None

diff --git a/src/disasm/print_intel.odin b/src/disasm/print_intel.odin
@@ -21,6 +21,12 @@ print_intel_rm_op :: proc(w: io.Writer, rm: RM_Op) -> (err: io.Error) {
         io.write_string(w, gpreg_name(rm.size, rm.reg)) or_return
     case .Mem_Addr_8, .Mem_Addr_16, .Mem_Addr_32:
         reg_size := u8(2) if rm.kind == .Mem_Addr_16 else 4
+        switch rm.size {
+        case 1: io.write_string(w, "byte ")
+        case 2: io.write_string(w, "word ")
+        case 4: io.write_string(w, "dword ")
+        case 8: io.write_string(w, "oword ")
+        }
         io.write_byte(w, '[')
         np := 0
         if rm.base_reg != REG_NONE {
@@ -62,25 +68,25 @@ print_intel_eop :: proc(w: io.Writer, addr: u64, inst: Instruction) -> (err: io.
     case .None: unreachable()
     case .Imm:
         switch eop.size {
-        case 1: fmt.wprintf(w, "%#.2x", eop.lo)
-        case 2: fmt.wprintf(w, "%#.4x", eop.lo)
-        case 4: fmt.wprintf(w, "%#.8x", eop.lo)
-        case 8: fmt.wprintf(w, "%#.16x", eop.lo)
+        case 1: fmt.wprintf(w, "%#02x", eop.lo)
+        case 2: fmt.wprintf(w, "%#04x", eop.lo)
+        case 4: fmt.wprintf(w, "%#08x", eop.lo)
+        case 8: fmt.wprintf(w, "%#016x", eop.lo)
         case: panic("Unkown extra operand size")
         }
     case .SAddr:
-        fmt.wprintf(w, "%#.2x", u8(eop.lo))
+        fmt.wprintf(w, "%#02x", u8(eop.lo))
     case .NAddr:
         switch eop.size {
-        case 2: fmt.wprintf(w, "%#.4x", u16(addr+u64(inst.size)+eop.lo))
-        case 4: fmt.wprintf(w, "%#.8x", u32(addr+u64(inst.size)+eop.lo))
+        case 2: fmt.wprintf(w, "%#04x", u16(addr+u64(inst.size)+eop.lo))
+        case 4: fmt.wprintf(w, "%#08x", u32(addr+u64(inst.size)+eop.lo))
         case: panic("Unknown extra operand size")
         }
     case .FAddr:
-        fmt.wprintf(w, "%#.2x:", eop.hi)
+        fmt.wprintf(w, "%#02x:", eop.hi)
         switch eop.size {
-        case 2: fmt.wprintf(w, "%#.4x", u16(eop.lo))
-        case 4: fmt.wprintf(w, "%#.8x", u32(eop.lo))
+        case 2: fmt.wprintf(w, "%#04x", u16(eop.lo))
+        case 4: fmt.wprintf(w, "%#08x", u32(eop.lo))
         case: panic("Unknown extra operand size")
         }
     }

diff --git a/src/disasm/print_nasm.odin b/src/disasm/print_nasm.odin