Added ultra96 board example

gatecat · Oct 10, 2020 · cc9948a · cc9948a
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diff --git a/xilinx/examples/ultra96/README.md b/xilinx/examples/ultra96/README.md
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+## Building the ultra96 example - RapidWright
+ - Run `java -jar rapidwright_bbaexport.jar xczu3eg-sbva484-1-e xilinx/constids.inc xilinx/xczu7ev.bba`
+ - Run `./bbasm xilinx/xczu3eg.bba xilinx/xczu3eg.bin -b`
+ - Run `blinky.sh` in `xilinx/examples/ultra96`.
+
diff --git a/xilinx/examples/ultra96/blinky.sh b/xilinx/examples/ultra96/blinky.sh
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+#!/usr/bin/env bash
+set -ex
+yosys -p "synth_xilinx -flatten -arch xcup -nobram -top top; write_json blinky.json" ../attosoc/attosoc.v blinky.v
+../../../nextpnr-xilinx --chipdb ../../xczu3eg.bin --json blinky.json --xdc ultra96.xdc --write blinky_routed.json
+java -jar ../../../rapidwright_json2dcp.jar xczu3eg-sbva484-1-e blinky_routed.json blinky.dcp
+vivado -mode batch -nojournal -nolog  -source blinky.tcl
diff --git a/xilinx/examples/ultra96/blinky.tcl b/xilinx/examples/ultra96/blinky.tcl
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+open_checkpoint blinky.dcp
+write_verilog -force blinky_out.v
+write_bitstream -force blinky.bit
diff --git a/xilinx/examples/ultra96/blinky.v b/xilinx/examples/ultra96/blinky.v
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+module top (input clk_p, clk_n, reset, output [3:0] led);
+    wire clk_i;
+    IBUFDS clk_ibuf (
+        .I(clk_p),
+        .IB(clk_n),
+        .O(clk_i)
+    );
+    BUFGCTRL bufg_i (
+        .I0(clk_i),
+        .CE0(1'b1),
+        .S0(1'b1),
+        .O(clk)
+    );
+
+//`define BLINKY
+`ifdef BLINKY
+    reg clkdiv;
+    reg [21:0] ctr;
+
+    always @(posedge clk) {clkdiv, ctr} <= ctr + 1'b1;
+
+    reg [3:0] led_r;
+
+    always @(posedge clk) begin
+        if (clkdiv)
+            led_r <= led_r - 1'b1;
+    end
+    assign led = led_r;
+`else
+    wire [7:0] soc_led;
+
+    attosoc soc_i(
+        .clk(clk),
+        .reset(reset),
+        .led(soc_led)
+    );
+
+    assign led = soc_led[3:0];
+`endif
+endmodule
diff --git a/xilinx/examples/ultra96/firmware.hex b/xilinx/examples/ultra96/firmware.hex
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diff --git a/xilinx/examples/ultra96/ultra96.xdc b/xilinx/examples/ultra96/ultra96.xdc
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+set_property LOC D5 [get_ports led[0]]
+set_property LOC D6 [get_ports led[1]]
+set_property LOC A5 [get_ports led[2]]
+set_property LOC B5 [get_ports led[3]]
+
+set_property IOSTANDARD LVCMOS33 [get_ports led[0]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[1]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[2]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[3]]
+
+set_property LOC M11 [get_ports reset]
+set_property IOSTANDARD LVCMOS33 [get_ports reset]
+
+set_property LOC F23 [get_ports clk_p]
+set_property LOC E23 [get_ports clk_n]
+set_property IOSTANDARD LVDS [get_ports clk_p]