Merge pull request #281 from harvard-edge/279-citation-missing

279 citation missing

contents/hw_acceleration/hw_acceleration.qmd

@@ -460,7 +460,7 @@ While suitable for intermittent inference, sustaining near-peak throughput for t
 
 In general, CPUs provide a readily available baseline, GPUs deliver broadly accessible acceleration, FPGAs offer programmability, and ASICs maximize efficiency for fixed functions. The optimal choice depends on the target application's scale, cost, flexibility, and other requirements.
 
-Although first developed for data center deployment, where [cite some benefit that Google cites], Google has also put considerable effort into developing Edge TPUs. These Edge TPUs maintain the inspiration from systolic arrays but are tailored to the limited resources accessible at the edge.
+Although first developed for data center deployment, Google has also put considerable effort into developing [Edge TPUs](https://cloud.google.com/edge-tpu). These Edge TPUs maintain the inspiration from systolic arrays but are tailored to the limited resources accessible at the edge.
 
 ## Hardware-Software Co-Design