Added draft PR of generator for strongARM comparator #338
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Draft PR
utkarsh5086
changed the title
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Can you please describe your design and provide more details in general? |
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I would advise against using smart route for these generators as it not as parameterizable as the "dumb" routes, and parameterization is what we're looking for here. Furthermore please look at routing widths to account for the routes through which more current would flow if the circuit was used |
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| #cross_coupled_load(gf180_mapped_pdk,2,0.5).show() | ||
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| def mystrongARM(pdk: MappedPDK, diffp_w, diffp_l, ccinv_col, clk_fing, reset_w, reset_l): |
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add more parameterization here, for the diffpair transistors' length, width,etc.
also add options for taprings, welltaps and such
| lvs_result = sky130_mapped_pdk.lvs_netgen(diffPair,'diffPair') | ||
| return diffPair | ||
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| diffPair(sky130_mapped_pdk,2,0.4).show() |
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remove this line once the PR is ready
| mystrongARM.add_ports(diffp_ref.get_ports_list(), prefix="strongARM_") | ||
| mystrongARM.add_ports(cross_couple_ref.get_ports_list(), prefix="strongARM_") | ||
| mystrongARM.add_ports(clk_nmos_ref.get_ports_list(), prefix="strongARM_clk_nmos_") | ||
| mystrongARM.add_ports(reset_pmos_ref1.get_ports_list(), prefix="strongARM_clk_reset_pmos_r_") | ||
| mystrongARM.add_ports(reset_pmos_ref2.get_ports_list(), prefix="strongARM_clk_reset_pmos_l_") |
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add ports after all the routing has been done, it is beneficial to include the routes' ports as well
| mystrongARM.add(cross_couple_ref) | ||
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| clk_nmos = nmos(pdk, width=4, fingers=clk_fing, rmult=1, with_substrate_tap=False, with_dnwell=False) |
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why did you decide default width to be 4 micron?
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Tried to clean lvs on diffPair subblock, lvs fails pin matching |
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@utkarsh5086 Are you still stuck here? |
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I cleared the symmetry errors in LVS. I also passed LVS manually editing the netlist. I will make some changes to the LVS script and add them here. |
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any updates on this @utkarsh5086? |
A single python file with complete strongARM layout. Four subcells in total: diff_pair, cross_coupled pair and nmos, pmos reset switches. Plan to pick diff_pair and X_coupled pair from the repo in the future. Currently having errors in LVS and trying to debug it.
I will add testbench and automation setup to complete the analog generator.