Chipathon2024 Mahowald-ers Cascode Common Source Block

[Sud-ana]

PR for a cascode common source . LVS is failing with Final result: Top level cell failed pin matching. Please review and let us know the function parameters for LVS.

[Sud-ana]

@chetanyagoyal / @srpathen ,
LVS check is failing for this cell with error as Top level cell failed pin matching. Could you kindly help review the pin assignment function so that LVS succeeds ?

`Circuit 1 contains 6 devices, Circuit 2 contains 2 devices. *** MISMATCH ***
Circuit 1 contains 10 nets, Circuit 2 contains 5 nets. *** MISMATCH ***

Final result:
Top level cell failed pin matching.

Logging to file "/tmp/tmp4n_a1thr/cascode_common_source_lvs_lvs.rpt" disabled
LVS Done.

Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.

Subcircuit pins:

Circuit 1: sky130_fd_pr__nfet_01v8	Circuit 2: sky130_fd_pr__nfet_01v8
1	1
2	2
3	3
4	4

---

Cell pin lists are equivalent.
Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
Flattening unmatched subcell Unnamed_c9b8b1be in circuit cascode_common_source_lvs (0)(1 instance)
Flattening unmatched subcell Unnamed_a576aef1 in circuit cascode_common_source_lvs (0)(1 instance)

Class cascode_common_source_lvs (0): Merged 8 parallel devices.
Subcircuit summary:

Circuit 1: cascode_common_source_lvs	Circuit 2: cascode_common_source_lvs
sky130_fd_pr__nfet_01v8 (14->6)	sky130_fd_pr__nfet_01v8 (20->2) **Mismatch
Number of devices: 6 Mismatch	Number of devices: 2 Mismatch
Number of nets: 10 Mismatch	Number of nets: 5 Mismatch

---

NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: cascode_common_source_lvs |Circuit 2: cascode_common_source_lvs

---

Net: w_n780_n522# |Net: IOUT
sky130_fd_pr__nfet_01v8/4 = 6 | sky130_fd_pr__nfet_01v8/(1|3) = 1
|
Net: /Unnamed_c9b8b1be_0/a_n370_n286# |Net: VSS
sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/(1|3) = 1
| sky130_fd_pr__nfet_01v8/4 = 2
|
Net: /Unnamed_a576aef1_0/a_n245_n286# |(no matching net)
sky130_fd_pr__nfet_01v8/(1|3) = 1 |
|
Net: /Unnamed_c9b8b1be_0/a_498_n286# |(no matching net)
sky130_fd_pr__nfet_01v8/(1|3) = 2 |
sky130_fd_pr__nfet_01v8/2 = 1 |
|
Net: /Unnamed_c9b8b1be_0/a_n718_n286# |(no matching net)
sky130_fd_pr__nfet_01v8/(1|3) = 2 |
sky130_fd_pr__nfet_01v8/2 = 1 |
|
Net: /Unnamed_a576aef1_0/a_498_n286# |(no matching net)
sky130_fd_pr__nfet_01v8/(1|3) = 2 |
sky130_fd_pr__nfet_01v8/2 = 1 |
|
Net: /Unnamed_a576aef1_0/a_n718_n286# |(no matching net)
sky130_fd_pr__nfet_01v8/(1|3) = 2 |
sky130_fd_pr__nfet_01v8/2 = 1 |

DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: cascode_common_source_lvs |Circuit 2: cascode_common_source_lvs

---

Instance: Unnamed_c9b8b1be_0/sky130_fd_pr_ |(no matching instance)
(1,3) = (3,3) |
2 = 3 |
4 = 6 |
|
|
Instance: Unnamed_c9b8b1be_0/sky130_fd_pr_ |(no matching instance)
(1,3) = (3,3) |
2 = 3 |
4 = 6 |
|
|
Instance: Unnamed_a576aef1_0/sky130_fd_pr_ |(no matching instance)
(1,3) = (3,3) |
2 = 3 |
4 = 6 |
|
|
Instance: Unnamed_a576aef1_0/sky130_fd_pr_ |(no matching instance)
(1,3) = (3,3) |
2 = 3 |
4 = 6 |
|

Netlists do not match.

Subcircuit pins:

Circuit 1: cascode_common_source_lvs	Circuit 2: cascode_common_source_lvs
(no matching pin)	VIN
(no matching pin)	VBIAS
(no matching pin)	VSS
(no matching pin)	IOUT
proxyIOUT	(no matching pin)

---

Cell pin lists for cascode_common_source_lvs and cascode_common_source_lvs altered to match.
Device classes cascode_common_source_lvs and cascode_common_source_lvs are equivalent.

Final result: Top level cell failed pin matching.
`

[Sud-ana]

I've added the rectangular Pins and labels using add_label() and align_comp_to_port(). As a result the label and rectangular ports are visible on metal 1 as shown below. However, LVS is still failing as the export component doesn't recognize the ports as components.

`
Subcircuit pins:

Circuit 1: sky130_fd_pr__nfet_01v8	Circuit 2: sky130_fd_pr__nfet_01v8
1	1
2	2
3	3
4	4

---

Subcircuit pins:

Circuit 1: cascode_common_source_lvs	Circuit 2: cascode_common_source_lvs
(no matching pin)	VIN
(no matching pin)	VBIAS
(no matching pin)	VSS
(no matching pin)	IOUT
proxyIOUT	(no matching pin)

---

Cell pin lists for cascode_common_source_lvs and cascode_common_source_lvs altered to match.
Device classes cascode_common_source_lvs and cascode_common_source_lvs are equivalent.

Final result: Top level cell failed pin matching.

`

[chetanyagoyal]

use this extraction script

[Sud-ana]

@chetanyagoyal could you kindly clarify the netlist function used for the LVS check as the lvs fail implies that the Netlist is not getting extracted with the correct pins.

` return Netlist(
circuit_name='',
nodes=['VIN', 'VBIAS', 'VSS', 'IOUT'],
source_netlist=source_netlist,
instance_format=instance_format,
parameters={
'model': model,
'width': width,
'length': length,
'mult': multipliers
}
)

`

Also the extract scipt gave the following error whenused with the gds

`
./extract.bash.tempate.sh: line 13: paropt: command not found

Magic 8.3 revision 464 - Compiled on Sat Mar 9 23:18:29 UTC 2024.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Using technology "minimum", version 0.0
Don't know how to read GDS-II:
Nothing in "cifinput" section of tech file.
Warning: There is nothing here to extract.
Total Nodes: 0
`

[chetanyagoyal]

@chetanyagoyal could you kindly clarify the netlist function used for the LVS check as the lvs fail implies that the Netlist is not getting extracted with the correct pins.

` return Netlist( circuit_name='', nodes=['VIN', 'VBIAS', 'VSS', 'IOUT'], source_netlist=source_netlist, instance_format=instance_format, parameters={ 'model': model, 'width': width, 'length': length, 'mult': multipliers } )

`

Also the extract scipt gave the following error whenused with the gds

` ./extract.bash.tempate.sh: line 13: paropt: command not found

Magic 8.3 revision 464 - Compiled on Sat Mar 9 23:18:29 UTC 2024. Starting magic under Tcl interpreter Using the terminal as the console. Using NULL graphics device. Processing system .magicrc file Using technology "minimum", version 0.0 Don't know how to read GDS-II: Nothing in "cifinput" section of tech file. Warning: There is nothing here to extract. Total Nodes: 0 `

Apologies for the late replies, you can just dump the netlist from the python function to a file (top_level.info['netlist'].generate_netlist() should return a string).

Try modifying the function until the dumped netlist matches your expectations

[chetanyagoyal]

Please address the comments and look through the code in the repo to debug, let us know if youre stuck after this

[Sud-ana]

LVS checks are in progress. Have added the ports to the layout .

LVS checks are still failing.
`Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.

Subcircuit pins:

Circuit 1: sky130_fd_pr__nfet_01v8	Circuit 2: sky130_fd_pr__nfet_01v8
1	1
2	2
3	3
4	4

---

Cell pin lists are equivalent.
Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.

Subcircuit summary:

Circuit 1: cascode_common_source_lvs	Circuit 2: cascode_common_source_lvs
sky130_fd_pr__nfet_01v8 (2)	sky130_fd_pr__nfet_01v8 (2)
Number of devices: 2	Number of devices: 2
Number of nets: 6 Mismatch	Number of nets: 5 Mismatch

---

NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: cascode_common_source_lvs |Circuit 2: cascode_common_source_lvs

---

Net: IOUT |Net: IOUT
sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/(1|3) = 1
|
Net: VSS |Net: VSS
sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/(1|3) = 1
| sky130_fd_pr__nfet_01v8/4 = 2
|
Net: w_n386_n737# |(no matching net)
sky130_fd_pr__nfet_01v8/4 = 2 |

Netlists do not match.

Subcircuit pins:

Circuit 1: cascode_common_source_lvs	Circuit 2: cascode_common_source_lvs
(no pins)	VBIAS Mismatch
(no matching pin)	VIN
(no matching pin)	VSS
(no matching pin)	IOUT
(no matching pin)	INT

---

Cell pin lists for cascode_common_source_lvs and cascode_common_source_lvs altered to match.
Device classes cascode_common_source_lvs and cascode_common_source_lvs are equivalent.

Final result: Top level cell failed pin matching.`

Unable to store the LVS, DRC results in DRC, LVS directory as I see error below
magic_drc_result = sky130.drc_magic(Cascode_cs_component, Cascode_cs_component.name, output_file_path="DRC/") File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/deprecated/decorator.py", line 55, in wrapper_function return vd.call(*args, **kwargs) File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/deprecated/decorator.py", line 149, in call m = self.init_model_instance(*args, **kwargs) File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/deprecated/decorator.py", line 146, in init_model_instance return self.model(**values) File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/main.py", line 209, in __init__ validated_self = self.__pydantic_validator__.validate_python(data, self_instance=self) File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/deprecated/decorator.py", line 255, in check_kwargs raise TypeError(f'unexpected keyword argument{plural}: {keys}') TypeError: unexpected keyword argument: 'output_file_path'