feat: add GenerateArbitraryRegFile func and update to 1.3-SNAPSHOT

build.sbt

@@ -2,7 +2,7 @@
 lazy val useCHA: Boolean =
   sys.props.getOrElse("CHA", "false").toLowerCase == "true"
 
-ThisBuild / version      := { if (useCHA) "1.1-cha-SNAPSHOT" else "1.1-SNAPSHOT" }
+ThisBuild / version      := { if (useCHA) "1.3-cha-SNAPSHOT" else "1.3-SNAPSHOT" }
 ThisBuild / organization := "cn.ac.ios.tis"
 ThisBuild / scalaVersion := "2.12.17"
 // Use Scala2.13 with ChiselTest0.6.0 will cause efficiency issues in the

src/main/scala/rvspeccore/checker/ConnectHelper.scala

@@ -20,6 +20,11 @@ object ConnectCheckerResult extends ConnectHelper {
   val uniqueIdEvent: String = "ConnectCheckerResult_UniqueIdEvent"
   val uniqueIdDTLB: String  = "ConnectCheckerResult_UniqueIdDTLB"
   val uniqueIdITLB: String  = "ConnectCheckerResult_UniqueIdITLB"
+  val uniqueIdRandom: String = "ConnectCheckerResult_UniqueIdRandom"
+
+  def setRandomTarget(randomVec: Vec[UInt]) = {
+    BoringUtils.addSink(randomVec, uniqueIdRandom)
+  }
   def setRegSource(regVec: Vec[UInt]) = {
     BoringUtils.addSource(regVec, uniqueIdReg)
   }
@@ -92,12 +97,14 @@ object ConnectCheckerResult extends ConnectHelper {
     event
   }
 
-  def setChecker(checker: CheckerWithResult, memDelay: Int = 0)(implicit XLEN: Int, config: RVConfig) = {
+  def setChecker(checker: CheckerWithResult, memDelay: Int = 0, init: Boolean = false)(implicit XLEN: Int, config: RVConfig) = {
     // reg
     val regVec = Wire(Vec(32, UInt(XLEN.W)))
     regVec := DontCare
     BoringUtils.addSink(regVec, uniqueIdReg)
+    val initval = if(init) WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) else GenerateArbitraryRegFile(XLEN)
 
+    BoringUtils.addSource(initval, uniqueIdRandom)
     checker.io.result.reg := regVec
     checker.io.result.pc  := DontCare
 

src/main/scala/rvspeccore/checker/RandomHelper.scala

@@ -0,0 +1,17 @@
+package rvspeccore.checker
+
+import chisel3._
+import chisel3.util._
+
+import rvspeccore.core.spec
+
+
+object GenerateArbitraryRegFile{
+    def apply(implicit XLEN: Int): Vec[UInt] = {
+        val rf = Wire(Vec(32, UInt(XLEN.W)))
+        rf.map(_:= DontCare)
+        rf(0) := 0.U
+        rf
+    }
+}
+

src/main/scala/rvspeccore/core/RiscvCore.scala

@@ -7,6 +7,7 @@ import spec._
 import spec.instset.csr.CSR
 import spec.instset.csr.EventSig
 import spec.instset.csr.SatpStruct
+import rvspeccore.checker.ConnectCheckerResult
 
 abstract class BaseCore()(implicit val config: RVConfig) extends Module {
   implicit val XLEN: Int = config.XLEN
@@ -75,7 +76,11 @@ object State {
   def wireInit()(implicit XLEN: Int, config: RVConfig): State = {
     val state = Wire(new State)
 
-    state.reg := Seq.fill(32)(0.U(XLEN.W))
+    val initval = Wire(Vec(32, UInt(XLEN.W)))
+    initval := DontCare
+    ConnectCheckerResult.setRandomTarget(initval)
+    state.reg := initval
+    // state.reg := Seq.fill(32)(0.U(XLEN.W))
     state.pc  := config.initValue.getOrElse("pc", "h8000_0000").U(XLEN.W)
     state.csr := CSR.wireInit()