CPU notes

docs/Public/Software/Computer Architecture/CISC.md

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+See: [[RISC]]
+
+*CISC*, which stands for *Complex Instruction Set*, describes a [[CPU]] architecture where there are different instructions that can accomplish all sorts of tasks.
+
+The thought process is that since hardware is so fast, we should provide instructions to do as much as we can in it so programmers can take advantage of them. 
+
+Providing these complex instructions can increase the worse case path, which slows down all instructions. 

docs/Public/Software/Computer Architecture/CPU.md

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+*CPUs* have a few different types of instruction formats to accommodate for all of the different operations while still maintaining some consistency. 
+
+Major components of a *CPU* are:
+- Program Counter: Stores the address of the instruction we are working on
+- Register File: Small amount of memory inside the CPU*. Stores values we are working on
+- [[ALU]]: Does the computations
+- Decoder: Reads instruction and sets the control signals inside of the *CPU* to make it do what the instruction says
+
+Some types of CPU:
+- [[MIPS CPU]]

docs/Public/Software/Computer Architecture/MIPS CPU.md

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+A *MIPS CPU* has the following:
+- Implements an [[RISC]] based architecture
+- Has a fixed size instruction format
+	- 32 bits for a 32 bit CPU and 64 bits for a 64 bit CPU
+- Has 3 major instruction formats
+	- R-Type
+	- I-Type
+	- J-Type

docs/Public/Software/Computer Architecture/cache.md

@@ -1 +1,22 @@
-A *cache* is a temporary [[data]] store that holds data so future requests for that data can be serve faster. 
+A *cache* is a temporary [[data]] store that holds data so future requests for that data can be serve faster. 
+
+It is a smaller, faster memory component inserted between the main memory and the [[CPU]] that stores values recently accessed in [[memory]].
+
+Requests to memory are intercepted to the cache:
+1. If the cache has it, it serves it immediately
+2. If the cache doesn't have it, it will make a request to memory and store the result for later
+
+The *cache* can be extended beyond the original use:
+- Main memory serves as a *cache* to the hard drive
+- Registers serve as a *cache* for the *cache*
+
+*Cache* is used for the internet a lot.
+
+Terminology:
+- Word: An element in memory
+	- The unit of transfer between the *cache* and the CPU
+- Block. A contiguous chunk (next to each other) of words in memory
+	- Unit of transfer between memory and the *cache*
+- Way: A Block inside of a set along with the additional overhead bits related to a block to make the *cache* work
+- Set: a collection of Ways
+- Cache: a collection of Sets

docs/Public/Software/Computer Architecture/clock edge.md

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+A *clock edge* acts as a sampling signal that triggers the update of a state element. 
+
+There is a rising *edge* and a falling *edge*. 
+
+One *edge* is called the active *edge* - the *edge* (rising or falling) on which changes occur. [^1]
+
+![[edge.png]]
+
+[^1]: https://cs.nyu.edu/~gottlieb/courses/2000s/2000-01-fall/arch/lectures/lecture-04.html

docs/Public/Software/Computer Architecture/clock skew.md

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+A *clock skew* describes how a clock does not arrive to all [[flip flop]] at the same time, as components can be far apart and clocks can be gated. 
+
+A *clock skew* limits the amount of useful work we can do. 

docs/Public/Software/Computer Architecture/instruction.md

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+An *instruction* is the basic elementary operations that a [[CPU]] can perform. [^1]
+
+There are different kinds of *instructions*:
+- R-Type *Instructions*
+	- Register *Instructions*
+	- rd = rs funct rt
+		- rd = destination
+		- rs = source
+		- rt = target
+		- funct = the bits of the instruction to perform
+- I-Type *Instructions*
+	- Immediate *Instruction*
+	- rt = rs op Sign Extended Immediate
+	- SEI means prepending the most significant bit of the immediate to the immediate until it is 32 bits big
+- J-Type *Instructions*
+	- Jump *Instructions*
+	- PC = (PC+4)_{31:28}:addr:00, where ':' means concatenate
+	- PC = program counter; the address of the *instruction* that we are currently working on right now
+
+[^1]: https://www.geeksforgeeks.org/computer-organization-basic-computer-instructions/

docs/Public/Software/Computer Architecture/one hot decoder.md

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+See: [[one hot encoder]]
+
 A *one hot decoder* has $n$ inputs and $2^n$ outputs, where each combination of inputs corresponds to an output of 1. 

docs/Public/Software/Computer Architecture/one hot encoder.md

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+See: [[one hot decoder]]
+
+A *one hot encoder* has one [[flip flop]] per state, and exactly one of these flip flops will be $1$ at a time. 
+
+Another way to think of it, is that you have a [[binary]] [[vector]] of length $n$, where the vector is all zeroes except for the index that corresponds to the category, which is set to $1$.
+
+For the three categories, "Red", "Green", and "Blue":
+- "Red": [1, 0, 0]
+- "Green": [0, 1, 0]
+- "Blue": [0, 0, 1]
+

docs/Public/Software/Operating Systems/stream cheat sheet.md

@@ -59,4 +59,10 @@ sort foo.txt | uniq -c  // Display frequency of each line
 echo 1 | sudo tee /sys/class/leds/input2::scrolllock/brightness
 ```
 
+`sed`: 
+- Stream editor
+- Allows for filtering, substitution, addition, and deletion of text from file
+```
+
+```