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chore: nit
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rkdud007 committed Nov 22, 2024
1 parent c333ef7 commit 57b6be9
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Showing 2 changed files with 6 additions and 19 deletions.
23 changes: 6 additions & 17 deletions crates/brainfuck_prover/src/components/processor/table.rs
Original file line number Diff line number Diff line change
Expand Up @@ -34,18 +34,6 @@ pub struct ProcessorTableRow {
mvi: BaseField,
}

impl ProcessorTableRow {
/// Creates a row for the [`ProcessorTable`] which is considered 'dummy'.
///
/// A 'dummy' row, is a row that is not part of the execution trace from the Brainfuck program
/// execution.
/// They are used for padding and filling the gaps after sorting by `clk`, to enforce the
/// correct sorting.
pub fn new_dummy(clk: BaseField, ip: BaseField) -> Self {
Self { clk, ip, ..Default::default() }
}
}

impl From<&Registers> for ProcessorTableRow {
fn from(registers: &Registers) -> Self {
Self {
Expand Down Expand Up @@ -111,10 +99,11 @@ impl ProcessorTable {
let trace_len = self.table.len();
let padding_offset = (trace_len.next_power_of_two() - trace_len) as u32;
for i in 1..=padding_offset {
self.add_row(ProcessorTableRow::new_dummy(
last_row.clk + BaseField::from(i),
last_row.ip,
));
self.add_row(ProcessorTableRow {
clk: last_row.clk + BaseField::from(i),
ip: last_row.ip,
..Default::default()
});
}
}
}
Expand All @@ -124,7 +113,7 @@ impl From<Vec<Registers>> for ProcessorTable {
fn from(registers: Vec<Registers>) -> Self {
let mut processor_table = Self::new();

let rows = registers.iter().map(|x| x.into()).collect();
let rows = registers.iter().map(Into::into).collect();
processor_table.add_rows(rows);
processor_table.pad();

Expand Down
2 changes: 0 additions & 2 deletions crates/brainfuck_vm/src/bin/brainfuck_vm.rs
Original file line number Diff line number Diff line change
Expand Up @@ -21,8 +21,6 @@ struct Args {
#[clap(long)]
trace: bool,
#[clap(long)]
pad_trace: bool,
#[clap(long)]
ram_size: Option<usize>,
}

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