Refactor/add hal as datastructure

aarch64_qemuvirt/src/main.rs

@@ -14,9 +14,15 @@ const LAUNCH_TESTS: bool = cfg!(feature = "launch_tests");
 
 use log::info;
 
+unsafe fn disable_fp_trapping() {
+    asm!("msr CPACR_EL1, {:x}", in(reg) 0b11 << 20)
+}
+
 #[no_mangle]
 extern "C" fn k_main(_device_tree_ptr: usize) -> ! {
-    kernel::hal::cpu::disable_fp_trapping();
+    unsafe {
+        disable_fp_trapping();
+    }
 
     static PL011: Pl011 = Pl011::new(0x0900_0000);
     kernel::kernel_console::set_earlyinit_console(&PL011);
@@ -25,9 +31,7 @@ extern "C" fn k_main(_device_tree_ptr: usize) -> ! {
 
     info!("hello, I am a goOSe! proud member of the gagelen !!!");
 
-    unsafe {
-        kernel::hal::irq::init_el1_exception_handlers();
-    }
+    kernel::HAL.init_irqs();
 
     unsafe {
         asm!("isb SY");

hal_aarch64/Cargo.toml

@@ -10,3 +10,4 @@ hal_core = { path = "../hal_core" }
 tock-registers = "0.8"
 cortex-a = "8.1"
 log = "0.4"
+spin = "0.9.8"

hal_aarch64/src/devices/gicv2.rs

@@ -2,13 +2,26 @@ use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
 use tock_registers::register_bitfields;
 use tock_registers::registers::{ReadOnly, ReadWrite};
 
+use core::fmt;
 use hal_core::Error;
 
 pub struct GicV2 {
     pub distributor: &'static GicDistributor,
     pub cpu: &'static GicCpu,
 }
 
+impl fmt::Debug for GicV2 {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_struct("GicV2")
+            .field(
+                "distributor",
+                &(self.distributor as *const GicDistributor as *const ()),
+            )
+            .field("cpu", &(self.cpu as *const _ as *const ()))
+            .finish()
+    }
+}
+
 impl GicV2 {
     pub fn new(distributor_base: usize, cpu_base: usize) -> Self {
         let distributor = unsafe {
@@ -17,32 +30,32 @@ impl GicV2 {
                 .unwrap()
         };
         let cpu = unsafe { (cpu_base as *const GicCpu).as_ref().unwrap() };
-        let mut gic = Self { distributor, cpu };
+        let gic = Self { distributor, cpu };
 
         gic.init_distributor();
 
         gic
     }
 
-    pub fn disable_interrupts(&mut self) {
+    pub fn disable_interrupts(&self) {
         self.distributor
             .CTLR
             .modify(GICD_CTLR::EnableGrp0::Disable + GICD_CTLR::EnableGrp1::Disable);
     }
 
-    pub fn enable_interrupts(&mut self) {
+    pub fn enable_interrupts(&self) {
         self.distributor
             .CTLR
             .modify(GICD_CTLR::EnableGrp0::Enable + GICD_CTLR::EnableGrp1::Enable);
     }
 
-    pub fn get_int(&mut self) -> Result<u32, Error> {
+    pub fn get_int(&self) -> Result<u32, Error> {
         let intno = self.cpu.IAR.get();
 
         Ok(intno)
     }
 
-    pub fn clear_int(&mut self, int: u32) {
+    pub fn clear_int(&self, int: u32) {
         // TODO: check (maybe in the TRM) if this could fail / give an error.
         self.cpu.EOIR.modify(GICC_EOIR::EOIINTID.val(int));
     }
@@ -54,7 +67,7 @@ impl GicV2 {
     }
 
     /// Put the Gic in a known state.
-    fn init_distributor(&mut self) {
+    fn init_distributor(&self) {
         self.disable_interrupts();
 
         for i in 0..(self.nlines() / 32) {
@@ -98,7 +111,7 @@ impl GicV2 {
         );
     }
 
-    pub fn enable_line(&mut self, line: u32) -> Result<(), Error> {
+    pub fn enable_line(&self, line: u32) -> Result<(), Error> {
         let line = line as usize;
         let enable_reg_index = line >> 5;
         let enable_bit: u32 = 1u32 << (line % 32);
@@ -159,6 +172,11 @@ pub struct GicDistributor {
     _impdef3: [u32; 12],
 }
 
+/// Safety:
+/// I don't think this benefits from locking, if two cores write to the same
+///     reg, afaik it will just send two packets to the GIC, the latter will just accept both.
+unsafe impl Sync for GicDistributor {}
+
 register_bitfields! {u32,
     pub GICD_CTLR [
         EnableGrp0 OFFSET(0) NUMBITS(1) [
@@ -227,6 +245,10 @@ pub struct GicCpu {
     pub AHPPIR: ReadWrite<u32>,
 }
 
+/// Safety:
+/// Already per-cpu (one page per cpu), not need to lock it.
+unsafe impl Sync for GicCpu {}
+
 register_bitfields! {u32,
     pub GICC_CTLR [
         EnableGrp0 OFFSET(0) NUMBITS(1) [