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feat(arch-ops): holeybytes upstream instruction sync
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@chorman0773
ondra05 authored and chorman0773 committed Oct 1, 2023
1 parent 1e94772 commit e194ad6
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7 changes: 1 addition & 6 deletions arch-ops/src/holeybytes/codec.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,7 @@ use {
super::{Instruction, Operands},
crate::{
holeybytes::{
OpsA, OpsO, OpsP, OpsRRA, OpsRRAH, OpsRRO, OpsRROH, OpsRRP, OpsRRPH, Relative16,
Relative32,
OpsO, OpsP, OpsRRA, OpsRRAH, OpsRRO, OpsRROH, OpsRRP, OpsRRPH, Relative16, Relative32,
},
traits::InsnWrite,
},
Expand Down Expand Up @@ -106,10 +105,6 @@ impl<W: InsnWrite> HbEncoder<W> {
self.write_all(&[r0.0, r1.0])?;
self.write_addr(16, addr, true)
},
Operands::OpsA(OpsA(addr)) => {
self.write_addr(64, addr, false)
},

Operands::OpsO(OpsO(Relative32(addr))) => {
self.write_addr(32, addr, true)
},
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99 changes: 50 additions & 49 deletions arch-ops/src/holeybytes/instructions.in
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Original file line number Diff line number Diff line change
@@ -1,46 +1,46 @@
// OPCODE, MNEMONIC, TYPE, DOC;

0, UN, N, "Cause an unreachable code trap" ;
1, TX, N, "Termiante execution" ;
2, NOP, N, "Do nothing" ;

3, ADD, RRR, "Addition" ;
4, SUB, RRR, "Subtraction" ;
5, MUL, RRR, "Multiplication" ;
6, AND, RRR, "Bitand" ;
7, OR, RRR, "Bitor" ;
8, XOR, RRR, "Bitxor" ;
9, SL, RRR, "Unsigned left bitshift" ;
0, UN, N, "Cause an unreachable code trap" ;
1, TX, N, "Termiante execution" ;
2, NOP, N, "Do nothing" ;

3, ADD, RRR, "Addition" ;
4, SUB, RRR, "Subtraction" ;
5, MUL, RRR, "Multiplication" ;
6, AND, RRR, "Bitand" ;
7, OR, RRR, "Bitor" ;
8, XOR, RRR, "Bitxor" ;
9, SL, RRR, "Unsigned left bitshift" ;
10, SR, RRR, "Unsigned right bitshift" ;
11, SRS, RRR, "Signed right bitshift" ;
12, CMP, RRR, "Signed comparsion" ;
13, CMPU, RRR, "Unsigned comparsion" ;
14, DIR, RRRR, "Merged divide-remainder" ;
15, NOT, RR, "Logical negation" ;
16, ADDI, RRD, "Addition with immediate" ;
17, MULI, RRD, "Multiplication with immediate" ;
18, ANDI, RRD, "Bitand with immediate" ;
19, ORI, RRD, "Bitor with immediate" ;
20, XORI, RRD, "Bitxor with immediate" ;
21, SLI, RRW, "Unsigned left bitshift with immedidate";
22, SRI, RRW, "Unsigned right bitshift with immediate";
23, SRSI, RRW, "Signed right bitshift with immediate" ;
24, CMPI, RRD, "Signed compare with immediate" ;
25, CMPUI, RRD, "Unsigned compare with immediate" ;
15, NEG, RR, "Bit negation" ;
16, NOT, RR, "Logical negation" ;
17, ADDI, RRD, "Addition with immediate" ;
18, MULI, RRD, "Multiplication with immediate" ;
19, ANDI, RRD, "Bitand with immediate" ;
20, ORI, RRD, "Bitor with immediate" ;
21, XORI, RRD, "Bitxor with immediate" ;
22, SLI, RRW, "Unsigned left bitshift with immedidate";
23, SRI, RRW, "Unsigned right bitshift with immediate";
24, SRSI, RRW, "Signed right bitshift with immediate" ;
25, CMPI, RRD, "Signed compare with immediate" ;
26, CMPUI, RRD, "Unsigned compare with immediate" ;

26, CP, RR, "Copy register" ;
27, SWA, RR, "Swap registers" ;
28, LI, RD, "Load immediate" ;
29, LRA, RRO, "Load relative address" ;
30, LD, RRAH, "Load from absolute address" ;
31, ST, RRAH, "Store to absolute address" ;
32, LDR, RROH, "Load from relative address" ;
33, STR, RROH, "Store to relative address" ;
34, BMC, RRH, "Copy block of memory" ;
35, BRC, RRB, "Copy register block" ;
27, CP, RR, "Copy register" ;
28, SWA, RR, "Swap registers" ;
29, LI, RD, "Load immediate" ;
30, LRA, RRO, "Load relative address" ;
31, LD, RRAH, "Load from absolute address" ;
32, ST, RRAH, "Store to absolute address" ;
33, LDR, RROH, "Load from relative address" ;
34, STR, RROH, "Store to relative address" ;
35, BMC, RRH, "Copy block of memory" ;
36, BRC, RRB, "Copy register block" ;

36, JMP, A, "Absolute jump" ;
37, JMPR, O, "Relative jump" ;
37, JMP, O, "Relative jump" ;
38, JAL, RRA, "Linking absolute jump" ;
39, JALR, RRO, "Linking relative jump" ;
40, JEQ, RRP, "Branch on equal" ;
Expand All @@ -49,21 +49,22 @@
43, JGT, RRP, "Branch on greater-than (signed)" ;
44, JLTU, RRP, "Branch on lesser-than (unsigned)" ;
45, JGTU, RRP, "Branch on greater-than (unsigned)" ;
46, ECALL, N, "Issue ecall trap" ;
46, ECA, N, "Environment call trap" ;
47, EBP, N, "Environment breakpoint" ;

47, ADDF, RRR, "Floating addition" ;
48, SUBF, RRR, "Floating subtraction" ;
49, MULF, RRR, "Floating multiply" ;
50, DIRF, RRRR, "Merged floating divide-remainder" ;
51, FMAF, RRRR, "Fused floating multiply-add" ;
52, NEGF, RR, "Floating sign negation" ;
53, ITF, RR, "Int to float" ;
54, FTI, RR, "Float to int" ;
48, ADDF, RRR, "Floating addition" ;
49, SUBF, RRR, "Floating subtraction" ;
50, MULF, RRR, "Floating multiply" ;
51, DIRF, RRRR, "Merged floating divide-remainder" ;
52, FMAF, RRRR, "Fused floating multiply-add" ;
53, NEGF, RR, "Floating sign negation" ;
54, ITF, RR, "Int to float" ;
55, FTI, RR, "Float to int" ;

55, ADDFI, RRD, "Floating addition with immediate" ;
56, MULFI, RRD, "Floating multiplication with immediate";
56, ADDFI, RRD, "Floating addition with immediate" ;
57, MULFI, RRD, "Floating multiplication with immediate";

57, LRA16 , RRP, "Load relative immediate (16 bit)" ;
58, LDR16 , RRPH, "Load from relative address (16 bit)" ;
59, STR16 , RRPH, "Store to relative address (16 bit)" ;
60, JMPR16, P, "Relative jump (16 bit)" ;
58, LRA16 , RRP, "Load relative immediate (16 bit)" ;
59, LDR16 , RRPH, "Load from relative address (16 bit)" ;
60, STR16 , RRPH, "Store to relative address (16 bit)" ;
61, JMPR16, P, "Relative jump (16 bit)" ;
1 change: 0 additions & 1 deletion arch-ops/src/holeybytes/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -153,7 +153,6 @@ define_operands! {
+ OpsRRPH (Register , Register, Relative16, u16 ),
+ OpsRRO (Register , Register, Relative32 ),
+ OpsRRP (Register , Register, Relative16 ),
+ OpsA (Address ),
+ OpsO (Relative32 ),
+ OpsP (Relative16 ),
= OpsN ( ),
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