fix(archops-x86): Set REX.W for Quad registers in OpRegGeneral

lccc-project · Aug 1, 2023 · ea2c7a1 · ea2c7a1
1 parent 009e025
commit ea2c7a1
Showing 1 changed file with 4 additions and 1 deletion.
diff --git a/arch-ops/src/x86/insn.rs b/arch-ops/src/x86/insn.rs
@@ -1986,7 +1986,10 @@ impl<W: InsnWrite> X86Encoder<W> {
                     | (X86RegisterClass::Double, X86Mode::Real | X86Mode::Virtual8086) => {
                         Some(0x66)
                     }
-                    (X86RegisterClass::Quad, X86Mode::Long) => None,
+                    (X86RegisterClass::Quad, X86Mode::Long) => {
+                        *rex.get_or_insert(0x40) |= 0x8;
+                        None
+                    }
                     (class, mode) => {
                         panic!("Unsupported register class {:?} in mode {:?}", class, mode)
                     }