Improve comments around check_mem_access and mmio_load/store #1724
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dv/cosim/spike_cosim.cc
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| } | ||
| // case). | ||
| uint32_t aligned_addr = addr & 0xfffffffc; | ||
| if ( pending_iside_error && |
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This does alter the behaviour from what it was previously. Now the address needs to the fail the 'is_probably_dmem_access' heuristic before we check if the address matches a pending iside error. Previously if it matched a pending iside error it automatically assumed it was an iside error.
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I've updated this to be an assertion failure if the is_probably_dmem_access and pending_iside_error are both true. I think it is probably better to be explicit about what happens when something goes wrong here. Does that make sense?
| // | ||
| // Spike may attempt to access up to 8-bytes from the PC when fetching, so | ||
| // assume as a dside access when it falls outside that range. | ||
| // N.B. Heuristic |
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Worth mentioning that is the heuristic doesn't get it right it will produce false failures. In general we don't expect to see the scenarios that generate such false failures in practise and if they prove to be an issue we'll rethink this mechanism.
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Rebased |
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Thanks for this @hcallahan-lowrisc, looks good once we've fixed up the assertion (see comment).
| bool is_probably_dmem_access = (addr < pc || addr >= (pc + 8)); | ||
| // Check we don't have a heuristic mismatch (this may be a false-positive but | ||
| // worth failing explicity if it is seen) | ||
| assert(!(is_probably_dmem_access && pending_iside_error)); |
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This also needs to check if the pending iside error address matches the incoming address (pending_iside_err_addr == aligned_addr check you can see below).
Maybe add a new bool that combines the two as it'll be used in a couple of places?
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Ah yes good point. Will do!
dv/cosim/spike_cosim.cc
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| } | ||
| // case). | ||
| uint32_t aligned_addr = addr & 0xfffffffc; | ||
| if ( pending_iside_error && |
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@hcallahan-lowrisc any progress on this? |
Not yet. Will try and get it closed soon. |
| // the access was iside-speculative. | ||
| // | ||
| // Whenever a load/store is attempted by spike, we check the following | ||
| // conditions.... |
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Nit: 4 dots instead of 3
| // 3) Check the type of spike access (load/store) matches that of the queued | ||
| // dmem access. | ||
| // | ||
| // If the dut dmem access was misaligned : |
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Nit: space before colon
| // | ||
| // If the top pending access from the DUT was the first half of a misaligned | ||
| // access which accesses the top byte, it must have crossed the 32-bit | ||
| // boundary and generated a second access |
Added more comments around the function of SpikeCosim::check_mem_access() and SpikeCosim::mmio_load()/mmio_store().
Minor refactoring for clarity and flow with the comments.
I guess it could be argued that this should be in the /doc directory, but I'm indifferent to either. Feedback welcome.