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LAA, LVer: add pre-commit tests for llvm#96656 (llvm#96925)
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The issue is in LoopAccessAnalysis, but the regression was seen in the
user LoopVersioning. Hence, add pre-commit tests for both, in
preparation to fix the issue in LoopAccessAnalysis.
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@artagnon @lravenclaw
artagnon authored and lravenclaw committed Jul 3, 2024
1 parent dc7bf09 commit 2611f5f
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49 changes: 49 additions & 0 deletions llvm/test/Analysis/LoopAccessAnalysis/pr96656.ll
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; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes='print<access-info>' -disable-output %s 2>&1 | FileCheck %s

define void @false.equal.predicate(ptr %arg, ptr %arg1, i1 %arg2) {
; CHECK-LABEL: 'false.equal.predicate'
; CHECK-NEXT: loop.body:
; CHECK-NEXT: Memory dependences are safe
; CHECK-NEXT: Dependences:
; CHECK-NEXT: Run-time memory checks:
; CHECK-NEXT: Grouped accesses:
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
; CHECK-NEXT: Equal predicate: %load == 1
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %gep10 = getelementptr double, ptr %gep8, i64 %mul:
; CHECK-NEXT: {(8 + %arg1),+,(8 * (sext i32 %load to i64))<nsw>}<%loop.body>
; CHECK-NEXT: --> {(8 + %arg1),+,8}<%loop.body>
;
entry:
%load = load i32, ptr %arg, align 4
br i1 %arg2, label %noloop.exit, label %loop.ph

loop.ph: ; preds = %entry
%sext7 = sext i32 %load to i64
%gep8 = getelementptr i8, ptr %arg1, i64 8
br label %loop.body

loop.body: ; preds = %loop.body, %loop.ph
%phi = phi i64 [ 0, %loop.ph ], [ %add, %loop.body ]
%mul = mul i64 %phi, %sext7
%gep10 = getelementptr double, ptr %gep8, i64 %mul
%load11 = load double, ptr %gep10, align 8
store double %load11, ptr %arg1, align 8
%add = add i64 %phi, 1
%icmp = icmp eq i64 %phi, 0
br i1 %icmp, label %loop.exit, label %loop.body

noloop.exit: ; preds = %entry
%sext = sext i32 %load to i64
%gep = getelementptr double, ptr %arg1, i64 %sext
%load5 = load double, ptr %gep, align 8
store double %load5, ptr %arg, align 8
ret void

loop.exit: ; preds = %loop.body
ret void
}
78 changes: 78 additions & 0 deletions llvm/test/Transforms/LoopVersioning/pr96656.ll
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes=loop-versioning -S %s | FileCheck %s

define void @lver.check.unnecessary(ptr %arg, ptr %arg1, i1 %arg2) {
; CHECK-LABEL: define void @lver.check.unnecessary(
; CHECK-SAME: ptr [[ARG:%.*]], ptr [[ARG1:%.*]], i1 [[ARG2:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr [[ARG]], align 4
; CHECK-NEXT: br i1 [[ARG2]], label %[[NOLOOP_EXIT:.*]], label %[[LOOP_BODY_LVER_CHECK:.*]]
; CHECK: [[LOOP_BODY_LVER_CHECK]]:
; CHECK-NEXT: [[SEXT7:%.*]] = sext i32 [[LOAD]] to i64
; CHECK-NEXT: [[GEP8:%.*]] = getelementptr i8, ptr [[ARG1]], i64 8
; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[LOAD]], 1
; CHECK-NEXT: br i1 [[IDENT_CHECK]], label %[[LOOP_BODY_PH_LVER_ORIG:.*]], label %[[LOOP_BODY_PH:.*]]
; CHECK: [[LOOP_BODY_PH_LVER_ORIG]]:
; CHECK-NEXT: br label %[[LOOP_BODY_LVER_ORIG:.*]]
; CHECK: [[LOOP_BODY_LVER_ORIG]]:
; CHECK-NEXT: [[PHI_LVER_ORIG:%.*]] = phi i64 [ 0, %[[LOOP_BODY_PH_LVER_ORIG]] ], [ [[ADD_LVER_ORIG:%.*]], %[[LOOP_BODY_LVER_ORIG]] ]
; CHECK-NEXT: [[MUL_LVER_ORIG:%.*]] = mul i64 [[PHI_LVER_ORIG]], [[SEXT7]]
; CHECK-NEXT: [[GEP10_LVER_ORIG:%.*]] = getelementptr double, ptr [[GEP8]], i64 [[MUL_LVER_ORIG]]
; CHECK-NEXT: [[LOAD11_LVER_ORIG:%.*]] = load double, ptr [[GEP10_LVER_ORIG]], align 8
; CHECK-NEXT: store double [[LOAD11_LVER_ORIG]], ptr [[ARG1]], align 8
; CHECK-NEXT: [[ADD_LVER_ORIG]] = add i64 [[PHI_LVER_ORIG]], 1
; CHECK-NEXT: [[ICMP_LVER_ORIG:%.*]] = icmp eq i64 [[PHI_LVER_ORIG]], 0
; CHECK-NEXT: br i1 [[ICMP_LVER_ORIG]], label %[[LOOP_EXIT_LOOPEXIT:.*]], label %[[LOOP_BODY_LVER_ORIG]]
; CHECK: [[LOOP_BODY_PH]]:
; CHECK-NEXT: br label %[[LOOP_BODY:.*]]
; CHECK: [[LOOP_BODY]]:
; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ 0, %[[LOOP_BODY_PH]] ], [ [[ADD:%.*]], %[[LOOP_BODY]] ]
; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[PHI]], [[SEXT7]]
; CHECK-NEXT: [[GEP10:%.*]] = getelementptr double, ptr [[GEP8]], i64 [[MUL]]
; CHECK-NEXT: [[LOAD11:%.*]] = load double, ptr [[GEP10]], align 8
; CHECK-NEXT: store double [[LOAD11]], ptr [[ARG1]], align 8
; CHECK-NEXT: [[ADD]] = add i64 [[PHI]], 1
; CHECK-NEXT: [[ICMP:%.*]] = icmp eq i64 [[PHI]], 0
; CHECK-NEXT: br i1 [[ICMP]], label %[[LOOP_EXIT_LOOPEXIT1:.*]], label %[[LOOP_BODY]]
; CHECK: [[NOLOOP_EXIT]]:
; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[LOAD]] to i64
; CHECK-NEXT: [[GEP:%.*]] = getelementptr double, ptr [[ARG1]], i64 [[SEXT]]
; CHECK-NEXT: [[LOAD5:%.*]] = load double, ptr [[GEP]], align 8
; CHECK-NEXT: store double [[LOAD5]], ptr [[ARG]], align 8
; CHECK-NEXT: ret void
; CHECK: [[LOOP_EXIT_LOOPEXIT]]:
; CHECK-NEXT: br label %[[LOOP_EXIT:.*]]
; CHECK: [[LOOP_EXIT_LOOPEXIT1]]:
; CHECK-NEXT: br label %[[LOOP_EXIT]]
; CHECK: [[LOOP_EXIT]]:
; CHECK-NEXT: ret void
;
entry:
%load = load i32, ptr %arg, align 4
br i1 %arg2, label %noloop.exit, label %loop.ph

loop.ph: ; preds = %entry
%sext7 = sext i32 %load to i64
%gep8 = getelementptr i8, ptr %arg1, i64 8
br label %loop.body

loop.body: ; preds = %loop.body, %loop.ph
%phi = phi i64 [ 0, %loop.ph ], [ %add, %loop.body ]
%mul = mul i64 %phi, %sext7
%gep10 = getelementptr double, ptr %gep8, i64 %mul
%load11 = load double, ptr %gep10, align 8
store double %load11, ptr %arg1, align 8
%add = add i64 %phi, 1
%icmp = icmp eq i64 %phi, 0
br i1 %icmp, label %loop.exit, label %loop.body

noloop.exit: ; preds = %entry
%sext = sext i32 %load to i64
%gep = getelementptr double, ptr %arg1, i64 %sext
%load5 = load double, ptr %gep, align 8
store double %load5, ptr %arg, align 8
ret void

loop.exit: ; preds = %loop.body
ret void
}

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