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Implement TOP instruction
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@lyrakisk
lyrakisk committed Nov 6, 2024
1 parent 201dac7 commit 5badb66
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Showing 2 changed files with 27 additions and 0 deletions.
20 changes: 20 additions & 0 deletions src/cpu/instructions.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -137,6 +137,7 @@ impl Instruction {
"STY" => sty(self, cpu),
"TAX" => tax(self, cpu),
"TAY" => tay(self, cpu),
"TOP" => top(self, cpu),
"TSX" => tsx(self, cpu),
"TXA" => txa(self, cpu),
"TXS" => txs(self, cpu),
Expand Down Expand Up @@ -325,6 +326,13 @@ pub static INSTRUCTIONS: Lazy<HashMap<u8, Instruction>> = Lazy::new(|| {
Instruction {opcode: 0x1B, name: "SLO", bytes: 3, addressing_mode: AddressingMode::Absolute_Y, cycles: 7},
Instruction {opcode: 0x03, name: "SLO", bytes: 2, addressing_mode: AddressingMode::Indexed_Indirect_X, cycles: 8},
Instruction {opcode: 0x13, name: "SLO", bytes: 2, addressing_mode: AddressingMode::Indirect_indexed_Y, cycles: 8},
Instruction {opcode: 0x0C, name: "TOP", bytes: 3, addressing_mode: AddressingMode::Absolute, cycles: 4},
Instruction {opcode: 0x1C, name: "TOP", bytes: 3, addressing_mode: AddressingMode::Absolute_X, cycles: 4},
Instruction {opcode: 0x3C, name: "TOP", bytes: 3, addressing_mode: AddressingMode::Absolute_X, cycles: 4},
Instruction {opcode: 0x5C, name: "TOP", bytes: 3, addressing_mode: AddressingMode::Absolute_X, cycles: 4},
Instruction {opcode: 0x7C, name: "TOP", bytes: 3, addressing_mode: AddressingMode::Absolute_X, cycles: 4},
Instruction {opcode: 0xDC, name: "TOP", bytes: 3, addressing_mode: AddressingMode::Absolute_X, cycles: 4},
Instruction {opcode: 0xFC, name: "TOP", bytes: 3, addressing_mode: AddressingMode::Absolute_X, cycles: 4},
]
.into_iter()
.map(|instruction| (instruction.opcode, instruction))
Expand Down Expand Up @@ -1086,6 +1094,18 @@ fn tay(instruction: &Instruction, cpu: &mut CPU) -> InstructionResult {
};
}

fn top(instruction: &Instruction, cpu: &mut CPU) -> InstructionResult {
let mut instruction_result = InstructionResult {
executed_cycles: instruction.cycles,
};

instruction_result.executed_cycles += instruction.addressing_mode.is_page_crossed(cpu) as u8;
nop(instruction, cpu);
nop(instruction, cpu);
nop(instruction, cpu);
return instruction_result;
}

fn tsx(instruction: &Instruction, cpu: &mut CPU) -> InstructionResult {
cpu.register_x = cpu.stack_pointer;
cpu.update_zero_flag(cpu.register_x);
Expand Down
7 changes: 7 additions & 0 deletions src/cpu/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -448,6 +448,7 @@ mod test_cpu {
#[test_case("submodules/65x02/nes6502/v1/09.json")]
#[test_case("submodules/65x02/nes6502/v1/0a.json")]
#[test_case("submodules/65x02/nes6502/v1/0b.json")]
#[test_case("submodules/65x02/nes6502/v1/0c.json")]
#[test_case("submodules/65x02/nes6502/v1/0d.json")]
#[test_case("submodules/65x02/nes6502/v1/0e.json")]
#[test_case("submodules/65x02/nes6502/v1/0f.json")]
Expand All @@ -461,6 +462,7 @@ mod test_cpu {
#[test_case("submodules/65x02/nes6502/v1/18.json")]
#[test_case("submodules/65x02/nes6502/v1/19.json")]
#[test_case("submodules/65x02/nes6502/v1/1b.json")]
#[test_case("submodules/65x02/nes6502/v1/1c.json")]
#[test_case("submodules/65x02/nes6502/v1/1d.json")]
#[test_case("submodules/65x02/nes6502/v1/1e.json")]
#[test_case("submodules/65x02/nes6502/v1/1f.json")]
Expand All @@ -483,6 +485,7 @@ mod test_cpu {
#[test_case("submodules/65x02/nes6502/v1/36.json")]
#[test_case("submodules/65x02/nes6502/v1/38.json")]
#[test_case("submodules/65x02/nes6502/v1/39.json")]
#[test_case("submodules/65x02/nes6502/v1/3c.json")]
#[test_case("submodules/65x02/nes6502/v1/3d.json")]
#[test_case("submodules/65x02/nes6502/v1/3e.json")]
#[test_case("submodules/65x02/nes6502/v1/40.json")]
Expand All @@ -503,6 +506,7 @@ mod test_cpu {
#[test_case("submodules/65x02/nes6502/v1/56.json")]
#[test_case("submodules/65x02/nes6502/v1/58.json")]
#[test_case("submodules/65x02/nes6502/v1/59.json")]
#[test_case("submodules/65x02/nes6502/v1/5c.json")]
#[test_case("submodules/65x02/nes6502/v1/5d.json")]
#[test_case("submodules/65x02/nes6502/v1/5e.json")]
#[test_case("submodules/65x02/nes6502/v1/60.json")]
Expand All @@ -523,6 +527,7 @@ mod test_cpu {
#[test_case("submodules/65x02/nes6502/v1/76.json")]
#[test_case("submodules/65x02/nes6502/v1/78.json")]
#[test_case("submodules/65x02/nes6502/v1/79.json")]
#[test_case("submodules/65x02/nes6502/v1/7c.json")]
#[test_case("submodules/65x02/nes6502/v1/7d.json")]
#[test_case("submodules/65x02/nes6502/v1/7e.json")]
#[test_case("submodules/65x02/nes6502/v1/80.json")]
Expand Down Expand Up @@ -588,6 +593,7 @@ mod test_cpu {
#[test_case("submodules/65x02/nes6502/v1/d6.json")]
#[test_case("submodules/65x02/nes6502/v1/d8.json")]
#[test_case("submodules/65x02/nes6502/v1/d9.json")]
#[test_case("submodules/65x02/nes6502/v1/dc.json")]
#[test_case("submodules/65x02/nes6502/v1/dd.json")]
#[test_case("submodules/65x02/nes6502/v1/de.json")]
#[test_case("submodules/65x02/nes6502/v1/e0.json")]
Expand All @@ -609,6 +615,7 @@ mod test_cpu {
#[test_case("submodules/65x02/nes6502/v1/f6.json")]
#[test_case("submodules/65x02/nes6502/v1/f8.json")]
#[test_case("submodules/65x02/nes6502/v1/f9.json")]
#[test_case("submodules/65x02/nes6502/v1/fc.json")]
#[test_case("submodules/65x02/nes6502/v1/fd.json")]
#[test_case("submodules/65x02/nes6502/v1/fe.json")]
fn run_test_from_json(path: &str) {
Expand Down

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