Auto-detect SVP

mist-devel · Jul 16, 2024 · 87c0805 · 87c0805
1 parent aa14fdf
commit 87c0805
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Showing 9 changed files with 176 additions and 41 deletions.
diff --git a/Board/mist/MIST_Toplevel.vhd b/Board/mist/MIST_Toplevel.vhd
@@ -209,7 +209,7 @@ signal bk_saveD : std_logic := '0';
 signal downloading      : std_logic;
 signal data_io_wr       : std_logic;
 signal data_io_clkref   : std_logic;
-signal data_io_d        : std_logic_vector(7 downto 0);
+signal data_io_d        : std_logic_vector(15 downto 0);
 signal downloadingD     : std_logic;
 signal downloadingD_MCLK: std_logic;
 signal d_state          : std_logic_vector(1 downto 0);
@@ -223,13 +223,6 @@ signal ext_data_ack     : std_logic := '0';
 signal ext_sw           : std_logic_vector( 15 downto 0); --DIP switches
 signal core_led         : std_logic;
 
-constant SVP_EN         : std_logic := '0';
-
-function core_name return string is
-begin
-	if SVP_EN = '1' then return "GEN_SVP"; else return "GENESIS"; end if;
-end function;
-
 function bool_to_sl(X:boolean) return std_logic is
 begin
 	if X then return '1'; else return '0'; end if;
@@ -246,8 +239,8 @@ constant CONF_DBG_STR : string := "";
 --    "O4,FM Sound,Enable,Disable;"&
 --    "O5,PSG Sound,Enable,Disable;";
 
-constant CONF_STR : string := core_name &
-    ";BINGENMD ;"&
+constant CONF_STR : string :=
+    "GENESIS;BINGENMD ;"&
     "S,SAV,Mount;"&
     "TE,Write Save RAM;"&
     SEP&
@@ -313,13 +306,14 @@ END COMPONENT;
 
 component data_io
     generic ( ROM_DIRECT_UPLOAD : boolean := false;
-              USE_QSPI : boolean := false
+              USE_QSPI : boolean := false;
+              DOUT_16 : boolean := true
         );
     port (  clk_sys        : in std_logic;
             clkref_n       : in std_logic;
             ioctl_wr       : out std_logic;
             ioctl_addr     : out std_logic_vector(24 downto 0);
-            ioctl_dout     : out std_logic_vector(7 downto 0);
+            ioctl_dout     : out std_logic_vector(15 downto 0);
             ioctl_download : out std_logic;
             ioctl_index    : out std_logic_vector(7 downto 0);
 
@@ -391,7 +385,6 @@ begin
 	end if;
 end process;
 
-ext_sw(1) <= SVP_EN; -- SVP
 ext_sw(3) <= status(5); --psg en
 ext_sw(4) <= status(4); --fm en
 ext_sw(5) <= status(7); --Export
@@ -906,13 +899,7 @@ begin
             case d_state is
             when "00" =>
                 if data_io_wr = '1' then
-                    ext_data(15 downto 8) <= data_io_d;
-                    data_io_clkref <= '1';
-                    d_state <= "01";
-                end if;
-            when "01" =>
-                if data_io_wr = '1' then
-                    ext_data(7 downto 0) <= data_io_d;
+                    ext_data <= data_io_d(7 downto 0) & data_io_d(15 downto 8);
                     data_io_clkref <= '0';
                     d_state <= "10";
                 end if;
@@ -924,6 +911,7 @@ begin
             when "11" =>
                 data_io_clkref <= '1';
                 d_state <= "00";
+            when others => null;
             end case;
         end if;
     end if;

diff --git a/Board/mist/fpgagen.qsf b/Board/mist/fpgagen.qsf
@@ -300,7 +300,7 @@ set_global_assignment -name SEED 1
 set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
 set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../../syn/mist
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
 set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING OFF
 set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
 set_global_assignment -name VERILOG_MACRO "FX68K_ALTERA_REGS=<None>"

diff --git a/src/SVP/SSP160x.vhd b/src/SVP/SSP160x.vhd
@@ -694,22 +694,31 @@ begin
 	RAMA_ADDR <= IR(7 downto 0) when INST.AS = IA_RAM or INST.AD = IA_RAM else RAMA_PTR;
 	RAMA_D <= std_logic_vector(unsigned(RAMA_Q) + 1) when INST.AS = IA_INDPTR else SRC_DATA;
 	RAMA_WE <= INST.RAM(0) and LAST_CYCLE and EN when INST.AD = IA_RAM or INST.AD = IA_PTR or INST.AS = IA_INDPTR else '0';
-
+
+	RAMA : entity work.dpram_dclk generic map(8, 16)
+	port map(
+		rdclock     => not CLK,
+		wrclock     => CLK,
+		rdaddress   => RAMA_ADDR,
+		wraddress   => RAMA_ADDR,
+		data        => RAMA_D,
+		q           => RAMA_Q,
+		wren        => RAMA_WE
+	);
+
 	RAMB_ADDR <= IR(7 downto 0) when INST.AS = IA_RAM or INST.AD = IA_RAM else RAMB_PTR;
 	RAMB_D <= std_logic_vector(unsigned(RAMB_Q) + 1) when INST.AS = IA_INDPTR else SRC_DATA;
 	RAMB_WE <= INST.RAM(1) and LAST_CYCLE and EN when INST.AD = IA_RAM or INST.AD = IA_PTR or INST.AS = IA_INDPTR else '0';
 
-	RAMAB : entity work.DualPortRAM generic map(9, 16)
+	RAMB : entity work.dpram_dclk generic map(8, 16)
 	port map(
-		clock     => not CLK,
-		address_a => '0' & RAMA_ADDR,
-		address_b => '1' & RAMB_ADDR,
-		data_a    => RAMA_D,
-		data_b    => RAMB_D,
-		q_a       => RAMA_Q,
-		q_b       => RAMB_Q,
-		wren_A    => RAMA_WE,
-		wren_B    => RAMB_WE
+		rdclock     => not CLK,
+		wrclock     => CLK,
+		rdaddress   => RAMB_ADDR,
+		wraddress   => RAMB_ADDR,
+		data        => RAMB_D,
+		q           => RAMB_Q,
+		wren        => RAMB_WE
 	);
 
 	PA <= IND_ADDR when IND_EXT_CYCLE = '1' else PC;

diff --git a/src/SVP/SVP.qip b/src/SVP/SVP.qip
@@ -1,3 +1,5 @@
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) SSP160x.vhd ]
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) SSP160x_PKG.vhd ]
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) SVP.vhd ]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dpram_dclk.vhd ]
+
diff --git a/src/SVP/dpram_dclk.vhd b/src/SVP/dpram_dclk.vhd
@@ -0,0 +1,53 @@
+-- Generic dual-port RAM implementation -
+-- will hopefully work for both Altera and Xilinx parts
+
+library ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+ENTITY dpram_dclk IS
+	GENERIC
+	(
+		addrbits : integer := 9;
+		databits : integer := 7
+	);
+	PORT
+	(
+		rdaddress		: IN STD_LOGIC_VECTOR (addrbits-1 downto 0);
+		wraddress		: IN STD_LOGIC_VECTOR (addrbits-1 downto 0);
+		rdclock		: IN STD_LOGIC  := '1';
+		wrclock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (databits-1 downto 0);
+		wren		: IN STD_LOGIC  := '0';
+		q		: OUT STD_LOGIC_VECTOR (databits-1 downto 0)
+	);
+END dpram_dclk;
+
+architecture arch of dpram_dclk is
+
+type ram_type is array(natural range ((2**addrbits)-1) downto 0) of std_logic_vector(databits-1 downto 0);
+shared variable ram : ram_type;
+
+begin
+
+-- Port A
+process (rdclock)
+begin
+	if (rdclock'event and rdclock = '1') then
+		q <= ram(to_integer(unsigned(rdaddress)));
+	end if;
+end process;
+
+-- Port B
+process (wrclock)
+begin
+	if (wrclock'event and wrclock = '1') then
+		if wren='1' then
+			ram(to_integer(unsigned(wraddress))) := data;
+		end if;
+	end if;
+end process;
+
+
+end architecture;
diff --git a/src/fpgagen_sdram.qip b/src/fpgagen_sdram.qip
@@ -1,6 +1,7 @@
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) fpgagen_sdram_top.vhd]
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) fpgagen_top.vhd]
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) os_rom.vhd]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) gen_cart.vhd]
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) gen_io.vhd]
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) gen_ctrl.vhd]
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) gen_lightgun.vhd]

diff --git a/src/fpgagen_sdram_top.vhd b/src/fpgagen_sdram_top.vhd
@@ -206,6 +206,8 @@ signal svp_rom_ack  : std_logic;
 signal svp_rom_a    : std_logic_vector(20 downto 1);
 signal svp_rom_q    : std_logic_vector(15 downto 0);
 
+signal svp_en       : std_logic;
+
 begin
 
 -- -----------------------------------------------------------------------
@@ -330,6 +332,20 @@ port map(
 	svp_rom_q    => svp_rom_q
 );
 
+gen_cart : entity work.gen_cart
+port map (
+	reset_n => reset_n,
+	MCLK         => MCLK,     --  54MHz
+	DL_CLK       => DL_CLK,
+
+	ext_reset_n  => ext_reset_n,
+	ext_bootdone => ext_bootdone,
+	ext_data     => ext_data,
+	ext_data_ack => ext_data_ack,
+
+	svp_en => svp_en
+);
+
 -- Genesis Core
 -- -----------------------------------------------------------------------
 -- -----------------------------------------------------------------------
@@ -382,7 +398,8 @@ port map (
 	ext_data_ack => ext_data_ack,
 
 	-- DIP switches
-	ext_sw       => ext_sw,
+	ext_sw       => ext_sw,
+	svp_en       => svp_en,
 
 	-- RAM/ROM interface
 	romwr_req    => romwr_req,

diff --git a/src/fpgagen_top.vhd b/src/fpgagen_top.vhd
@@ -103,6 +103,8 @@ port(
 	                                                   -- 14 - CPU Turbo
 	                                                   -- 15 - Border
 	                                                   -- 0 - CRAM dots
+
+	svp_en         : in std_logic;
 
 	-- RAM/ROM control
 	romwr_req : buffer std_logic;
@@ -223,7 +225,6 @@ type svprc_t is ( SVPRC_IDLE, SVPRC_FX68, SVPRC_DMA);
 signal SVPRC : svprc_t;
 
 signal SVP_CLKEN    : std_logic;
-signal SVP_ENABLE   : std_logic;
 
 signal SVP_DI       : std_logic_vector(15 downto 0);
 signal SVP_DO       : std_logic_vector(15 downto 0);
@@ -828,9 +829,8 @@ port map(
 	snd_right   => DAC_RDATA
 );
 
-SVP_ENABLE <= SW(1);
 -- SVP at A15000-A1500F
-FX68_SVP_SEL <= '1' when SVP_ENABLE = '1' and FX68_SEL = '1' and FX68_A(23 downto 4) = x"A1500" else '0';
+FX68_SVP_SEL <= '1' when svp_en = '1' and FX68_SEL = '1' and FX68_A(23 downto 4) = x"A1500" else '0';
 T80_SVP_SEL <= '1' when BAR(23 downto 15) = x"A1"&'0' and T80_A(15 downto 4) = x"500" and T80_MREQ_N = '0' and (T80_RD_N = '0' or T80_WR_N = '0') else '0';
 SVP_SEL <= T80_SVP_SEL or FX68_SVP_SEL;
 SVP_RNW <= T80_WR_N when T80_SVP_SEL = '1' else FX68_RNW when FX68_SVP_SEL = '1' else '1';
@@ -842,7 +842,7 @@ port map (
 	CLK         => MCLK,
 	CE          => SVP_CLKEN,
 	RST_N       => MRST_N,
-	ENABLE      => SVP_ENABLE,
+	ENABLE      => svp_en,
 
 	BUS_A       => SVP_A,
 	BUS_DO      => SVP_DO,
@@ -1602,7 +1602,7 @@ begin
 					FX68_FLASH_ACK <= '1';
 					FC <= FC_FX68_RD;
 				elsif DMA_FLASH_SEL = '1' and DMA_FLASH_DTACK_N = '1' then
-					if SVP_ENABLE = '1' then
+					if svp_en = '1' then
 						dma_a := VBUS_ADDR - 1;
 					else
 						dma_a := VBUS_ADDR;
@@ -1777,7 +1777,7 @@ end process;
 
 -- SRAM at 0x200000 - 20FFFF
 -- EEPROM at 0x200000
-SRAM_EN <= (SRAM_EN_AUTO or SRAM_EN_PAGEIN) and not SVP_ENABLE;
+SRAM_EN <= (SRAM_EN_AUTO or SRAM_EN_PAGEIN) and not svp_en;
 
 FX68_SRAM_SEL <= '1' when SRAM_EN = '1' and FX68_AS_N = '0' and FX68_A(23 downto 16) = x"20" and FX68_EEPROM_SEL = '0' else '0';
 FX68_EEPROM_SEL <= '1' when EEPROM_EN = '1' and FX68_SEL = '1' and FX68_A(23 downto 4) = x"20000" and FX68_A(3 downto 1) = "000" else '0';
@@ -1891,8 +1891,8 @@ end process;
 -- 300000-37FFFF - 128K mirrored x4
 -- 390000-39FFFF - cell arrange 1
 -- 3A0000-3AFFFF - cell arrange 2
-FX68_SVP_RAM_SEL <= '1' when SVP_ENABLE = '1' and (FX68_A(23 downto 19) = x"3"&'0' or FX68_A(23 downto 16) = x"39" or FX68_A(23 downto 16) = x"3A") and FX68_AS_N = '0' else '0';
-DMA_SVP_RAM_SEL <= '1' when SVP_ENABLE = '1' and (VBUS_ADDR(23 downto 19) = x"3"&'0' or VBUS_ADDR(23 downto 16) = x"39" or VBUS_ADDR(23 downto 16) = x"3A") and VBUS_SEL = '1' else '0';
+FX68_SVP_RAM_SEL <= '1' when svp_en = '1' and (FX68_A(23 downto 19) = x"3"&'0' or FX68_A(23 downto 16) = x"39" or FX68_A(23 downto 16) = x"3A") and FX68_AS_N = '0' else '0';
+DMA_SVP_RAM_SEL <= '1' when svp_en = '1' and (VBUS_ADDR(23 downto 19) = x"3"&'0' or VBUS_ADDR(23 downto 16) = x"39" or VBUS_ADDR(23 downto 16) = x"3A") and VBUS_SEL = '1' else '0';
 
 process( MRST_N, MCLK )
 variable svp_dma_a: std_logic_vector(23 downto 1);

diff --git a/src/gen_cart.vhd b/src/gen_cart.vhd
@@ -0,0 +1,65 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+
+entity gen_cart is
+port(
+	reset_n        : in std_logic;
+	MCLK           : in std_logic;  -- 54MHz
+	DL_CLK         : in std_logic;
+
+	ext_reset_n  : in std_logic := '1';
+	ext_bootdone : in std_logic := '0';
+	ext_data     : in std_logic_vector(15 downto 0) := (others => '0');
+	ext_data_ack : in std_logic := '0';
+
+	svp_en       : out std_logic
+);
+
+end entity;
+
+
+architecture rtl of gen_cart is
+
+signal romwr_a : unsigned(23 downto 1);
+signal cart_id : std_logic_vector(87 downto 0);
+
+function to_slv(s: string) return std_logic_vector is
+  constant ss: string(1 to s'length) := s;
+  variable rval: std_logic_vector(1 to 8 * s'length);
+  variable p: integer;
+  variable c: integer;
+begin
+  for i in ss'range loop
+    p := 8 * i;
+    c := character'pos(ss(i));
+    rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8));
+  end loop;
+  return rval;
+end function;
+
+begin
+
+	process (DL_CLK) begin
+		if rising_edge( DL_CLK ) then
+			if ext_reset_n = '0' then
+				romwr_a <= (others => '0');
+				svp_en <= '0';
+			elsif ext_data_ack = '1' then
+				romwr_a <= romwr_a + 1;
+				if(romwr_a = 384/2) then cart_id(87 downto 72) <= ext_data; end if;
+				if(romwr_a = 386/2) then cart_id(71 downto 56) <= ext_data; end if;
+				if(romwr_a = 388/2) then cart_id(55 downto 40) <= ext_data; end if;
+				if(romwr_a = 390/2) then cart_id(39 downto 24) <= ext_data; end if;
+				if(romwr_a = 392/2) then cart_id(23 downto  8) <= ext_data; end if;
+				if(romwr_a = 394/2) then cart_id( 7 downto  0) <= ext_data(15 downto 8); end if;
+			elsif ext_bootdone = '1' then
+				if   (cart_id(63 downto 0) = to_slv("MK-1229 ")) then svp_en <= '1';    -- Virtua Racing EU/US
+				elsif(cart_id(63 downto 0) = to_slv("G-7001  ")) then svp_en <= '1';    -- Virtua Racing JP
+				end if;
+			end if;
+		end if;
+	end process;
+
+end rtl;