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{ | ||
"BACKGROUND_PROGRAMMING" : "off", | ||
"COMPRESS" : false, | ||
"CPU" : true, | ||
"CRC_CHECK" : true, | ||
"Clock_Route_Order" : 0, | ||
"Convert_SDP32_36_to_SDP16_18" : true, | ||
"Correct_Hold_Violation" : true, | ||
"DONE" : false, | ||
"DOWNLOAD_SPEED" : "default", | ||
"Disable_Insert_Pad" : false, | ||
"ENABLE_CTP" : false, | ||
"ENABLE_MERGE_MODE" : false, | ||
"ENCRYPTION_KEY" : false, | ||
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", | ||
"ERROR_DECTION_AND_CORRECTION" : false, | ||
"ERROR_DECTION_ONLY" : false, | ||
"ERROR_INJECTION" : false, | ||
"EXTERNAL_MASTER_CONFIG_CLOCK" : false, | ||
"Enable_DSRM" : false, | ||
"FORMAT" : "binary", | ||
"FREQUENCY_DIVIDER" : "1", | ||
"Generate_Constraint_File_of_Ports" : false, | ||
"Generate_IBIS_File" : false, | ||
"Generate_Plain_Text_Timing_Report" : false, | ||
"Generate_Post_PNR_Simulation_Model_File" : false, | ||
"Generate_Post_Place_File" : false, | ||
"Generate_SDF_File" : false, | ||
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false, | ||
"Global_Freq" : "default", | ||
"GwSyn_Loop_Limit" : 2000, | ||
"HOTBOOT" : false, | ||
"I2C" : false, | ||
"I2C_SLAVE_ADDR" : "00", | ||
"INCREMENTAL_PLACE_AND_ROUTING" : "0", | ||
"INCREMENTAL_PLACE_ONLY" : "0", | ||
"IncludePath" : [ | ||
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], | ||
"Incremental_Compile" : "", | ||
"Initialize_Primitives" : false, | ||
"JTAG" : false, | ||
"MODE_IO" : false, | ||
"MSPI" : true, | ||
"MSPI_JUMP" : false, | ||
"MULTIBOOT_ADDRESS_WIDTH" : "24", | ||
"MULTIBOOT_MODE" : "Normal", | ||
"MULTIBOOT_SPI_FLASH_ADDRESS" : "000000", | ||
"MULTIJUMP_ADDRESS_WIDTH" : "24", | ||
"MULTIJUMP_MODE" : "Normal", | ||
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000", | ||
"Multi_Boot" : false, | ||
"OUTPUT_BASE_NAME" : "nes", | ||
"POWER_ON_RESET_MONITOR" : true, | ||
"PRINT_BSRAM_VALUE" : true, | ||
"PROGRAM_DONE_BYPASS" : false, | ||
"PlaceInRegToIob" : true, | ||
"PlaceIoRegToIob" : true, | ||
"PlaceOutRegToIob" : true, | ||
"Place_Option" : "2", | ||
"Process_Configuration_Verion" : "1.0", | ||
"Promote_Physical_Constraint_Warning_to_Error" : true, | ||
"READY" : false, | ||
"RECONFIG_N" : false, | ||
"Ram_RW_Check" : true, | ||
"Replicate_Resources" : false, | ||
"Report_Auto-Placed_Io_Information" : false, | ||
"Route_Maxfan" : 23, | ||
"Route_Option" : "0", | ||
"Run_Timing_Driven" : true, | ||
"SECURE_MODE" : false, | ||
"SECURITY_BIT" : true, | ||
"SEU_HANDLER" : false, | ||
"SEU_HANDLER_CHECKSUM" : false, | ||
"SEU_HANDLER_MODE" : "auto", | ||
"SSPI" : true, | ||
"STOP_SEU_HANDLER" : false, | ||
"Show_All_Warnings" : false, | ||
"Synthesize_tool" : "GowinSyn", | ||
"TclPre" : "", | ||
"TopModule" : "nestang_top", | ||
"USERCODE" : "default", | ||
"Unused_Pin" : "As_input_tri_stated_with_pull_up", | ||
"VCC" : "0.9", | ||
"VCCAUX" : "3.3", | ||
"VCCX" : "3.3", | ||
"VHDL_Standard" : "VHDL_Std_1993", | ||
"Verilog_Standard" : "Vlg_Std_Sysv2017", | ||
"WAKE_UP" : "0", | ||
"show_all_warnings" : false, | ||
"turn_off_bg" : false | ||
} |
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<?xml version="1" encoding="UTF-8"?> | ||
<!DOCTYPE gowin-fpga-project> | ||
<Project> | ||
<Template>FPGA</Template> | ||
<Version>5</Version> | ||
<Device name="GW5AT-60B" pn="GW5AT-LV60PG484AC1/I0">gw5at60b-002</Device> | ||
<FileList> | ||
<File path="src/EEPROM_24C0x.sv" type="file.verilog" enable="1"/> | ||
<File path="src/apu.v" type="file.verilog" enable="1"/> | ||
<File path="src/autofire.v" type="file.verilog" enable="1"/> | ||
<File path="src/cart.sv" type="file.verilog" enable="1"/> | ||
<File path="src/compat.v" type="file.verilog" enable="1"/> | ||
<File path="src/controller_ds2.sv" type="file.verilog" enable="1"/> | ||
<File path="src/controller_snes.v" type="file.verilog" enable="1"/> | ||
<File path="src/dpram.v" type="file.verilog" enable="1"/> | ||
<File path="src/dualshock_controller.v" type="file.verilog" enable="1"/> | ||
<File path="src/game_loader.v" type="file.verilog" enable="1"/> | ||
<File path="src/hdmi2/audio_clock_regeneration_packet.sv" type="file.verilog" enable="1"/> | ||
<File path="src/hdmi2/audio_info_frame.sv" type="file.verilog" enable="1"/> | ||
<File path="src/hdmi2/audio_sample_packet.sv" type="file.verilog" enable="1"/> | ||
<File path="src/hdmi2/auxiliary_video_information_info_frame.sv" type="file.verilog" enable="1"/> | ||
<File path="src/hdmi2/hdmi.sv" type="file.verilog" enable="1"/> | ||
<File path="src/hdmi2/packet_assembler.sv" type="file.verilog" enable="1"/> | ||
<File path="src/hdmi2/packet_picker.sv" type="file.verilog" enable="1"/> | ||
<File path="src/hdmi2/serializer.sv" type="file.verilog" enable="1"/> | ||
<File path="src/hdmi2/source_product_description_info_frame.sv" type="file.verilog" enable="1"/> | ||
<File path="src/hdmi2/tmds_channel.sv" type="file.verilog" enable="1"/> | ||
<File path="src/hw_uart.v" type="file.verilog" enable="1"/> | ||
<File path="src/iosys/gowin_dpb_menu.v" type="file.verilog" enable="1"/> | ||
<File path="src/iosys/iosys.v" type="file.verilog" enable="1"/> | ||
<File path="src/iosys/picorv32.v" type="file.verilog" enable="1"/> | ||
<File path="src/iosys/simplespimaster.v" type="file.verilog" enable="1"/> | ||
<File path="src/iosys/simpleuart.v" type="file.verilog" enable="1"/> | ||
<File path="src/iosys/spi_master.v" type="file.verilog" enable="1"/> | ||
<File path="src/iosys/spiflash.v" type="file.verilog" enable="1"/> | ||
<File path="src/iosys/textdisp.v" type="file.verilog" enable="1"/> | ||
<File path="src/mappers/JYCompany.sv" type="file.verilog" enable="1"/> | ||
<File path="src/mappers/MMC1.sv" type="file.verilog" enable="1"/> | ||
<File path="src/mappers/MMC2.sv" type="file.verilog" enable="1"/> | ||
<File path="src/mappers/MMC3.sv" type="file.verilog" enable="1"/> | ||
<File path="src/mappers/MMC5.sv" type="file.verilog" enable="1"/> | ||
<File path="src/mappers/Namco.sv" type="file.verilog" enable="1"/> | ||
<File path="src/mappers/Sachen.sv" type="file.verilog" enable="1"/> | ||
<File path="src/mappers/Sunsoft.sv" type="file.verilog" enable="1"/> | ||
<File path="src/mappers/generic.sv" type="file.verilog" enable="1"/> | ||
<File path="src/mappers/iir_filter.v" type="file.verilog" enable="1"/> | ||
<File path="src/mappers/misc.sv" type="file.verilog" enable="1"/> | ||
<File path="src/mega60k/config.v" type="file.verilog" enable="1"/> | ||
<File path="src/nes.v" type="file.verilog" enable="1"/> | ||
<File path="src/nes2hdmi.sv" type="file.verilog" enable="1"/> | ||
<File path="src/nestang_top.sv" type="file.verilog" enable="1"/> | ||
<File path="src/ppu.v" type="file.verilog" enable="1"/> | ||
<File path="src/primer25k/gowin_pll_27.v" type="file.verilog" enable="1"/> | ||
<File path="src/primer25k/gowin_pll_hdmi.v" type="file.verilog" enable="1"/> | ||
<File path="src/primer25k/gowin_pll_nes.v" type="file.verilog" enable="1"/> | ||
<File path="src/sdram_nes.v" type="file.verilog" enable="1"/> | ||
<File path="src/t65/T65.v" type="file.verilog" enable="1"/> | ||
<File path="src/t65/T65_ALU.v" type="file.verilog" enable="1"/> | ||
<File path="src/t65/T65_MCode.v" type="file.verilog" enable="1"/> | ||
<File path="src/t65/T65_Pack.v" type="file.verilog" enable="1"/> | ||
<File path="src/uart_tx_V2.v" type="file.verilog" enable="1"/> | ||
<File path="src/usb_hid_host.v" type="file.verilog" enable="1"/> | ||
<File path="src/usb_hid_host_rom.v" type="file.verilog" enable="1"/> | ||
<File path="src/mega60k/nestang.cst" type="file.cst" enable="1"/> | ||
<File path="src/primer25k/nestang.cst" type="file.cst" enable="0"/> | ||
<File path="src/primer25k/nestang_snescontroller.cst" type="file.cst" enable="0"/> | ||
<File path="src/primer25k/nestang.sdc" type="file.sdc" enable="1"/> | ||
<File path="src/nes.gao" type="file.gao" enable="0"/> | ||
</FileList> | ||
</Project> |
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`define RES_720P | ||
`define GW_IDE | ||
`define MEGA60K | ||
`define PRIMER | ||
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`define CONTROLLER_DS2 | ||
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package configPackage; | ||
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// Tang SDRAM v1.2: 2B * 8K * 512 * 4 = 32MB | ||
localparam SDRAM_DATA_WIDTH = 16; // 2 bytes per word | ||
localparam SDRAM_ROW_WIDTH = 13; // 8K rows | ||
localparam SDRAM_COL_WIDTH = 9; // 512 cols | ||
localparam SDRAM_BANK_WIDTH = 2; // 4 banks | ||
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endpackage |
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