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src/OneWare.UniversalFpgaProjectSystem/Services/NodeProviderService.cs
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Original file line number | Diff line number | Diff line change |
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using System.Text.RegularExpressions; | ||
using OneWare.Shared.Models; | ||
using OneWare.UniversalFpgaProjectSystem.Fpga; | ||
using OneWare.UniversalFpgaProjectSystem.Services; | ||
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namespace OneWare.Verilog.Parsing; | ||
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public class VerilogNodeProvider : INodeProvider | ||
{ | ||
public IEnumerable<FpgaNode> ExtractNodes(IProjectFile file) | ||
{ | ||
string fileContent = File.ReadAllText(file.FullPath); | ||
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// Regex, um die Modul-Deklaration zu finden und die Ports zu extrahieren | ||
string modulePattern = @"module\s+\w+\s*\((.*?)\);"; | ||
Match moduleMatch = Regex.Match(fileContent, modulePattern, RegexOptions.Singleline); | ||
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if (moduleMatch.Success) | ||
{ | ||
// Extrahieren der Ports innerhalb des Moduls | ||
string portSection = moduleMatch.Groups[1].Value; | ||
return ExtractAndPrintPorts(portSection); | ||
} | ||
return new List<FpgaNode>(); | ||
} | ||
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private static IEnumerable<FpgaNode> ExtractAndPrintPorts(string portSection) | ||
{ | ||
// Regex, um einzelne Port-Deklarationen zu identifizieren | ||
string portPattern = @"(input|output|inout)(\s*\[\d+:\d+\])?\s+([^;,]+)"; | ||
MatchCollection portMatches = Regex.Matches(portSection, portPattern, RegexOptions.Singleline); | ||
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foreach (Match match in portMatches) | ||
{ | ||
string portType = match.Groups[1].Value; | ||
string vectorSize = match.Groups[2].Value.Trim(); | ||
string[] portNames = match.Groups[3].Value.Split(new char[] { ',', ' ' }, StringSplitOptions.RemoveEmptyEntries); | ||
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foreach (string portName in portNames) | ||
{ | ||
Console.WriteLine($"Port: {portName}, Type: {portType}, Vector Size: {vectorSize}"); | ||
yield return new FpgaNode(portName, portType); | ||
} | ||
} | ||
} | ||
} |
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