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    • SystemVerilog
      Apache License 2.0
      61510Updated Dec 15, 2024Dec 15, 2024
    • renode

      Public
      Renode - virtual development tool for multinode embedded networks
      RobotFramework
      Other
      2973000Updated Dec 13, 2024Dec 13, 2024
    • tlib

      Public
      C++
      Other
      311603Updated Dec 13, 2024Dec 13, 2024
    • verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      C++
      GNU Lesser General Public License v3.0
      6232000Updated Dec 13, 2024Dec 13, 2024
    • rdfm

      Public
      Python
      Apache License 2.0
      62000Updated Dec 13, 2024Dec 13, 2024
    • CMake
      Apache License 2.0
      2401Updated Dec 13, 2024Dec 13, 2024
    • Apache License 2.0
      1200Updated Dec 13, 2024Dec 13, 2024
    • VeeR EL2 Core
      SystemVerilog
      Apache License 2.0
      75201Updated Dec 13, 2024Dec 13, 2024
    • C
      Apache License 2.0
      0000Updated Dec 13, 2024Dec 13, 2024
    • Python
      Apache License 2.0
      3400Updated Dec 13, 2024Dec 13, 2024
    • SCSS
      Apache License 2.0
      3000Updated Dec 13, 2024Dec 13, 2024
    • Python
      Apache License 2.0
      0100Updated Dec 12, 2024Dec 12, 2024
    • Makefile
      Apache License 2.0
      0100Updated Dec 12, 2024Dec 12, 2024
    • pigweed

      Public
      C++
      Apache License 2.0
      1101Updated Dec 12, 2024Dec 12, 2024
    • BitBake
      Apache License 2.0
      41720Updated Dec 12, 2024Dec 12, 2024
    • JavaScript
      Apache License 2.0
      31001Updated Dec 12, 2024Dec 12, 2024
    • pyrenode3

      Public
      Python
      Apache License 2.0
      62180Updated Dec 12, 2024Dec 12, 2024
    • dts2repl

      Public
      Python
      Apache License 2.0
      62121Updated Dec 12, 2024Dec 12, 2024
    • Vue
      Apache License 2.0
      51710Updated Dec 12, 2024Dec 12, 2024
    • FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
      Jupyter Notebook
      ISC License
      1131010Updated Dec 12, 2024Dec 12, 2024
    • OpenROAD

      Public
      OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
      Verilog
      BSD 3-Clause "New" or "Revised" License
      574100Updated Dec 11, 2024Dec 11, 2024
    • xls

      Public
      XLS: Accelerated HW Synthesis
      C++
      Apache License 2.0
      182000Updated Dec 11, 2024Dec 11, 2024
    • 0000Updated Dec 11, 2024Dec 11, 2024
    • riscv-dv

      Public
      SV/UVM based instruction generator for RISC-V processor verification
      Python
      Apache License 2.0
      331000Updated Dec 11, 2024Dec 11, 2024
    • Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
      Starlark
      Apache License 2.0
      45000Updated Dec 11, 2024Dec 11, 2024
    • Python
      Apache License 2.0
      21100Updated Dec 11, 2024Dec 11, 2024
    • raviewer

      Public
      Raw image/video data analyzer
      Python
      Apache License 2.0
      34420Updated Dec 11, 2024Dec 11, 2024
    • Python
      Apache License 2.0
      0100Updated Dec 10, 2024Dec 10, 2024
    • topwrap

      Public
      A Python package for generating HDL wrappers and top modules for HDL sources
      Python
      Apache License 2.0
      32310Updated Dec 10, 2024Dec 10, 2024
    • RobotFramework
      Apache License 2.0
      2112Updated Dec 9, 2024Dec 9, 2024