Align verif probes to bugs correction. #192
pascalgouedoAnnotations
3 errors and 1 warning
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Format Verilog Sources:
rtl/cv32e40p_mult.sv#L1
Files differ (M)
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Format Verilog Sources
Found differences, run util/format-verible before committing.
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Process completed with exit code 1.
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The following actions uses node12 which is deprecated and will be forced to run on node16: actions/checkout@v2, actions/setup-python@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
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