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@meggiman meggiman released this 14 Dec 18:04
· 290 commits to master since this release
v6.0.0
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Learn about vigilant mode.

Changed

  • Bump pulp_soc to v2.0.0 which adds completely new interconnect with integrated AXI crossbar for simplified IP
    integration
  • Make number of SPI and I2C peripherals parametrizable
  • Various FPGA tcl script enhancements
  • Various rtl code cleanups and assertion additions

Added

  • Fixed synthesis issues. PULPissimo is now synthesizable as is.
  • Revamped datasheet & added datasheet generator
  • CI support for pulp-runtime to run tests, using bwruntest.py and
    tests/runtime-tests.yaml
  • CI target for all supported fpga boards
  • Point to simple runtime in README.md
  • Allow passing generate-scripts to pass arguments to vlog
    ⁻ Add global address space header file for new SoC interconnect in pulp_soc v2.0.0
  • Embedded bootcode into repository and added new make target for it
  • FPGA support for Nexys board familly
  • Add pulp-sdk build target

Fixed

  • Properly propagate NB_CORES
  • Mark tb as not synthesizable
  • Add proper timing constraints for CDCs in FPGA port
  • Added missing implementation of manual clock gating cells for FPGA ports
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