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Merge pull request #1301 from qiboteam/fix_transpiler
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Small fix in transpiler initial and final layout
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andrea-pasquale authored May 2, 2024
2 parents 24acee0 + cdcd96c commit 703af36
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Showing 2 changed files with 24 additions and 3 deletions.
17 changes: 14 additions & 3 deletions src/qibo/transpiler/pipeline.py
Original file line number Diff line number Diff line change
Expand Up @@ -180,6 +180,8 @@ class Passes:
Defaults to :math:`qibo.transpiler.unroller.NativeGates.default`.
on_qubits (list, optional): list of physical qubits to be used.
If "None" all qubits are used. Defaults to ``None``.
int_qubit_name (bool, optional): if `True` the `final_layout` keys are
cast to integers.
"""

def __init__(
Expand All @@ -188,12 +190,15 @@ def __init__(
connectivity: nx.Graph = None,
native_gates: NativeGates = NativeGates.default(),
on_qubits: list = None,
int_qubit_names: bool = False,
):
if on_qubits is not None:
connectivity = restrict_connectivity_qubits(connectivity, on_qubits)
self.connectivity = connectivity
self.native_gates = native_gates
self.passes = self.default() if passes is None else passes
self.initial_layout = None
self.int_qubit_names = int_qubit_names

def default(self):
"""Return the default transpiler pipeline for the required hardware connectivity."""
Expand All @@ -215,8 +220,12 @@ def default(self):
return default_passes

def __call__(self, circuit):
self.initial_layout = None
final_layout = None
"""
This function returns the compiled circuits and the dictionary mapping
physical (keys) to logical (values) qubit. If `int_qubit_name` is `True`
each key `i` correspond to the `i-th` qubit in the graph.
"""
final_layout = self.initial_layout
for transpiler_pass in self.passes:
if isinstance(transpiler_pass, Optimizer):
transpiler_pass.connectivity = self.connectivity
Expand Down Expand Up @@ -247,7 +256,9 @@ def __call__(self, circuit):
TranspilerPipelineError,
f"Unrecognised transpiler pass: {transpiler_pass}",
)

# TODO: use directly integers keys
if self.int_qubit_names:
final_layout = {int(key[1:]): value for key, value in final_layout.items()}
return circuit, final_layout

def is_satisfied(self, circuit: Circuit):
Expand Down
10 changes: 10 additions & 0 deletions tests/test_transpiler_pipeline.py
Original file line number Diff line number Diff line change
Expand Up @@ -129,6 +129,16 @@ def test_assert_circuit_equivalence_false():
assert_circuit_equivalence(circ1, circ2, final_map=final_map)


def test_int_qubit_names():
circ = Circuit(2)
final_map = {i: i for i in range(5)}
default_transpiler = Passes(
passes=None, connectivity=star_connectivity(), int_qubit_names=True
)
_, final_layout = default_transpiler(circ)
assert final_map == final_layout


def test_assert_circuit_equivalence_wrong_nqubits():
circ1 = Circuit(1)
circ2 = Circuit(2)
Expand Down

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