Try #322:

.cargo/config

@@ -1,6 +1,7 @@
 [target.'cfg(all(target_arch = "arm", target_os = "none"))']
 runner = "gdb-multiarch -q -x openocd.gdb"
 rustflags = [
+    "-C", "link-arg=--nmagic",
     "-C", "link-arg=-Tlink.x",
 # The target (below) defaults to cortex-m4
 # There currently are two different options to go beyond that:

.github/workflows/ci.yml

@@ -16,6 +16,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v2
+      - run: sudo apt install gcc-arm-none-eabi
       - uses: actions-rs/toolchain@v1
         with:
           toolchain: stable
@@ -51,6 +52,7 @@ jobs:
             features: nightly
     steps:
       - uses: actions/checkout@v2
+      - run: sudo apt install gcc-arm-none-eabi
       - uses: actions-rs/toolchain@v1
         with:
           toolchain: ${{ matrix.toolchain }}

.github/workflows/release.yml

@@ -12,6 +12,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v2
+      - run: sudo apt install gcc-arm-none-eabi
       - uses: actions-rs/toolchain@v1
         with:
           toolchain: stable

Cargo.toml

@@ -56,6 +56,13 @@ rev = "61933f857a"
 features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"]
 version = "0.9.0"
 
+[build-dependencies]
+cc = "1.0"
+
+[patch.crates-io.cortex-m-rt]
+git = "https://github.com/rust-embedded/cortex-m-rt.git"
+rev = "a2e3ad5"
+
 [patch.crates-io.miniconf]
 git = "https://github.com/quartiq/miniconf.git"
 rev = "c6f2b28"

build.rs

@@ -0,0 +1,6 @@
+fn main() {
+    println!("cargo:rerun-if-changed=memory.x");
+
+    cc::Build::new().file("src/startup.S").compile("startup");
+    println!("cargo:rerun-if-changed=src/startup.S");
+}

memory.x

@@ -13,10 +13,6 @@ MEMORY
 }
 
 SECTIONS {
-  .itcm : ALIGN(8) {
-    *(.itcm .itcm.*);
-    . = ALIGN(8);
-    } > ITCM
   .axisram (NOLOAD) : ALIGN(8) {
     *(.axisram .axisram.*);
     . = ALIGN(8);
@@ -33,4 +29,18 @@ SECTIONS {
     *(.sram3 .sram3.*);
     . = ALIGN(4);
     } > SRAM3
-} INSERT AFTER .bss;
+  .itcm : ALIGN(8) {
+    . = ALIGN(8);
+    __sitcm = .;
+    *(.itcm .itcm.*);
+    . = ALIGN(8);
+    __eitcm = .;
+  } > ITCM AT>FLASH
+  __siitcm = LOADADDR(.itcm);
+} INSERT AFTER .uninit;
+
+ASSERT(__sitcm % 8 == 0 && __eitcm % 8 == 0, "
+BUG(cortex-m-rt): .itcm is not 8-byte aligned");
+
+ASSERT(__siitcm % 4 == 0, "
+BUG(cortex-m-rt): the LMA of .itcm is not 4-byte aligned");

src/bin/dual-iir.rs

@@ -120,6 +120,8 @@ const APP: () = {
     /// Because the ADC and DAC operate at the same rate, these two constraints actually implement
     /// the same time bounds, meeting one also means the other is also met.
     #[task(binds=DMA1_STR4, resources=[adcs, digital_inputs, dacs, iir_state, settings, telemetry], priority=2)]
+    #[inline(never)]
+    #[link_section = ".itcm.process"]
     fn process(c: process::Context) {
         let adc_samples = [
             c.resources.adcs.0.acquire_buffer(),

src/bin/lockin.rs

@@ -158,6 +158,8 @@ const APP: () = {
     /// It outputs either I/Q or power/phase on DAC0/DAC1. Data is normalized to full scale.
     /// PLL bandwidth, filter bandwidth, slope, and x/y or power/phase post-filters are available.
     #[task(binds=DMA1_STR4, resources=[adcs, dacs, lockin, timestamper, pll, settings, telemetry], priority=2)]
+    #[inline(never)]
+    #[link_section = ".itcm.process"]
     fn process(c: process::Context) {
         let adc_samples = [
             c.resources.adcs.0.acquire_buffer(),

src/hardware/mod.rs

@@ -73,11 +73,11 @@ fn panic(_info: &core::panic::PanicInfo) -> ! {
 }
 
 #[cortex_m_rt::exception]
-fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
+unsafe fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
     panic!("HardFault at {:#?}", ef);
 }
 
 #[cortex_m_rt::exception]
-fn DefaultHandler(irqn: i16) {
+unsafe fn DefaultHandler(irqn: i16) {
     panic!("Unhandled exception (IRQn = {})", irqn);
 }

src/startup.S

@@ -0,0 +1,44 @@
+.cfi_sections .debug_frame
+
+# .thumb
+.section .text.pre_init, "ax"
+.globl __pre_init
+.type __pre_init,%function
+.thumb_func
+.cfi_startproc
+__pre_init:
+
+  # Enable ITCM and DTCM
+  ldr r0, =1
+  ldr r1, =0xE000EF90
+  ldr r2, [r1]
+  # Set ITCMCR.EN
+  orr r2, r2, r0
+  str r2, [r1]
+  ldr r1, =0xE000EF94
+  ldr r2, [r1]
+  # Set DTCMCR.EN
+  orr r2, r2, r0
+  str r2, [r1]
+  dsb
+  isb
+
+  # Analogous to cortex-m-rt Reset code for .data copying.
+  # Initialise .itcm code. `__sitcm`, `__siitcm`, and `__eitcm` come from the
+  # linker script. Copy from r2 into r0 until r0 reaches r1.
+  ldr r0,=__sitcm
+  ldr r1,=__eitcm
+  ldr r2,=__siitcm
+1:
+  cmp r1, r0
+  beq 2f
+  # load 1 word from r2 to r3, inc r2
+  ldm r2!, {r3}
+  # store 1 word from r3 to r0, inc r0
+  stm r0!, {r3}
+  b 1b
+2:
+  dsb
+  isb
+  bx lr
+.cfi_endproc