Update

aarch64/src/devcons.rs

@@ -2,6 +2,7 @@
 
 use crate::param::KZERO;
 use crate::uartmini::MiniUart;
+use core::cell::SyncUnsafeCell;
 use core::mem::MaybeUninit;
 use port::devcons::Console;
 use port::fdt::DeviceTree;
@@ -36,10 +37,12 @@ pub fn init(dt: &DeviceTree) {
         let uart = MiniUart::new(dt, KZERO);
         uart.init();
 
-        static mut UART: MaybeUninit<MiniUart> = MaybeUninit::uninit();
+        static UART: SyncUnsafeCell<MaybeUninit<MiniUart>> =
+            SyncUnsafeCell::new(MaybeUninit::uninit());
         unsafe {
-            UART.write(uart);
-            UART.assume_init_mut()
+            let cons = &mut *UART.get();
+            cons.write(uart);
+            cons.assume_init_mut()
         }
     });
 }

aarch64/src/mailbox.rs

@@ -1,5 +1,6 @@
 use crate::io::{read_reg, write_reg};
 use crate::param::KZERO;
+use core::cell::SyncUnsafeCell;
 use core::mem::MaybeUninit;
 use port::fdt::DeviceTree;
 use port::mcslock::{Lock, LockNode};
@@ -21,10 +22,12 @@ pub fn init(dt: &DeviceTree) {
     let node = LockNode::new();
     let mut mailbox = MAILBOX.lock(&node);
     *mailbox = Some({
-        static mut MAYBE_MAILBOX: MaybeUninit<Mailbox> = MaybeUninit::uninit();
+        static MAYBE_MAILBOX: SyncUnsafeCell<MaybeUninit<Mailbox>> =
+            SyncUnsafeCell::new(MaybeUninit::uninit());
         unsafe {
-            MAYBE_MAILBOX.write(Mailbox::new(dt, KZERO));
-            MAYBE_MAILBOX.assume_init_mut()
+            let maybe_mailbox = &mut *MAYBE_MAILBOX.get();
+            maybe_mailbox.write(Mailbox::new(dt, KZERO));
+            maybe_mailbox.assume_init_mut()
         }
     });
 }

aarch64/src/main.rs

@@ -5,6 +5,7 @@
 #![feature(alloc_error_handler)]
 #![feature(core_intrinsics)]
 #![feature(strict_provenance)]
+#![feature(sync_unsafe_cell)]
 #![forbid(unsafe_op_in_unsafe_fn)]
 
 mod devcons;

port/src/allocator.rs

@@ -5,6 +5,8 @@
 // license that can be found in the LICENSE file or at
 // https://opensource.org/licenses/MIT.
 
+#![allow(clippy::too_long_first_doc_paragraph)]
+
 use alloc::alloc::{AllocError, Allocator, Layout};
 use core::ptr::NonNull;
 use core::sync::atomic::{AtomicUsize, Ordering};

port/src/fdt.rs

@@ -1,3 +1,5 @@
+#![allow(clippy::too_long_first_doc_paragraph)]
+
 use core::{
     ffi::CStr,
     mem::{self, MaybeUninit},
@@ -173,7 +175,7 @@ impl<'a> DeviceTree<'a> {
             }
             let (start, end) = (value_i, value_i + 4);
             value_i = end;
-            return self.structs().get(start..end).and_then(bytes_to_u32);
+            self.structs().get(start..end).and_then(bytes_to_u32)
         })
     }
 

riscv64/Cargo.toml

@@ -11,3 +11,6 @@ port = { path = "../port" }
 
 [features]
 opensbi = []
+
+[lints.rust]
+unexpected_cfgs = { level = "warn", check-cfg = ['cfg(platform, values("nezha"))', 'cfg(platform, values("virt"))'] }

riscv64/src/main.rs

@@ -1,4 +1,5 @@
 #![feature(alloc_error_handler)]
+#![feature(sync_unsafe_cell)]
 #![cfg_attr(not(any(test)), no_std)]
 #![cfg_attr(not(test), no_main)]
 #![allow(clippy::upper_case_acronyms)]

riscv64/src/platform/virt/devcons.rs

@@ -1,5 +1,6 @@
 // Racy to start.
 
+use core::cell::SyncUnsafeCell;
 use core::mem::MaybeUninit;
 
 use crate::uart16550::Uart16550;
@@ -17,11 +18,12 @@ pub fn init(dt: &DeviceTree) {
         let mut uart = Uart16550::new(ns16550a_reg);
         uart.init(115_200);
 
-        static mut UART: MaybeUninit<Uart16550> = MaybeUninit::uninit();
-
+        static CONS: SyncUnsafeCell<MaybeUninit<Uart16550>> =
+            SyncUnsafeCell::new(MaybeUninit::uninit());
         unsafe {
-            UART.write(uart);
-            UART.assume_init_mut()
+            let cons = &mut *CONS.get();
+            cons.write(uart);
+            cons.assume_init_mut()
         }
     });
 }

x86_64/src/devcons.rs

@@ -15,7 +15,7 @@ impl Uart for Uart16550 {
 
 pub fn init() {
     Console::new(|| {
-        static UART: SyncUnsafeCell<Uart16550> = SyncUnsafeCell::new(Uart16550 { port: 0x3f8 });
-        unsafe { &mut *UART.get() }
+        static CONS: SyncUnsafeCell<Uart16550> = SyncUnsafeCell::new(Uart16550 { port: 0x3f8 });
+        unsafe { &mut *CONS.get() }
     });
 }

x86_64/src/uart16550.rs

@@ -1,4 +1,4 @@
-/// Simple UART driver to get setarted.
+//! Simple UART driver to get started.
 
 pub fn putb(port: u16, b: u8) {
     unsafe {

xtask/src/config.rs

@@ -46,8 +46,6 @@ pub struct Build {
 /// #[cfg(dev_foo = "baz")]
 /// pub mod foobaz;
 /// ```
-
-/// config section
 #[derive(Debug, Serialize, Deserialize)]
 pub struct Config {
     pub dev: Option<Vec<String>>,