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Update processors from latest ghidra
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@radare
radare committed Jul 2, 2022
1 parent 47026fb commit 06dee4a
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8 changes: 4 additions & 4 deletions src/Processors/68000/data/languages/68000.sinc
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Expand Up @@ -2054,10 +2054,10 @@ fdivrnd: "d" is fopmode=0x64 {}
:flognp1.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x06; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
:flognp1 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x06 unimpl

:fmod.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0& fdst & $(FPREC_BWLS) & fopmode=0x2d; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
:fmod.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0& fdst & $(FPREC_XP) & fopmode=0x2d; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
:fmod.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0& fdst & $(FPREC_D) & fopmode=0x2d; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
:fmod fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x2d unimpl
:fmod.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0& fdst & $(FPREC_BWLS) & fopmode=0x21; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
:fmod.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0& fdst & $(FPREC_XP) & fopmode=0x21; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
:fmod.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0& fdst & $(FPREC_D) & fopmode=0x21; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
:fmod fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x21 unimpl


:fmove.b e2b, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fopmode=0x00 & ffmt=6; e2b
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3 changes: 3 additions & 0 deletions src/Processors/AARCH64/data/languages/AARCH64.cspec
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Expand Up @@ -127,6 +127,9 @@
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
<pentry minsize="9" maxsize="16" extension="zero">
<addr space="join" piece1="x1" piece2="x0"/>
</pentry>
</output>
<unaffected>
<register name="x19"/>
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1 change: 1 addition & 0 deletions src/Processors/ARM/data/languages/ARM7_be.slaspec
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Expand Up @@ -10,6 +10,7 @@
@define VERSION_7M ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""

@include "ARM.sinc"

1 change: 1 addition & 0 deletions src/Processors/ARM/data/languages/ARM7_le.slaspec
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Expand Up @@ -10,6 +10,7 @@
@define VERSION_7M ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""

@include "ARM.sinc"

1 change: 1 addition & 0 deletions src/Processors/ARM/data/languages/ARM8_be.slaspec
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Expand Up @@ -11,6 +11,7 @@
@define VERSION_8 ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""

@include "ARM.sinc"

1 change: 1 addition & 0 deletions src/Processors/ARM/data/languages/ARM8_le.slaspec
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Expand Up @@ -11,6 +11,7 @@
@define VERSION_8 ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""

@include "ARM.sinc"

524 changes: 263 additions & 261 deletions src/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
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380 changes: 194 additions & 186 deletions src/Processors/ARM/data/languages/ARMinstructions.sinc
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82 changes: 81 additions & 1 deletion src/Processors/ARM/data/languages/ARMneon.sinc
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Expand Up @@ -1784,7 +1784,7 @@ extImm: "#"^thv_c0811 is TMode=1 & thv_c0811 { tmp:1 = thv_c0811; export tmp; }
}


:vraddhn.i^esize2021x2 Dd,Qn,Qm is (($(AMODE) & cond=15 & c2527=1 & c2323=0 & c2021<3 & c0811=4 & Q6=0 & c0404=0) |
:vraddhn.i^esize2021x2 Dd,Qn,Qm is (($(AMODE) & cond=15 & c2527=1 & c2323=1 & c2021<3 & c0811=4 & Q6=0 & c0404=0) |
($(TMODE_F) & thv_c2327=0x1f & thv_c2021<3 & thv_c0811=4 & thv_Q6=0 & thv_c0404=0) ) & Qm & esize2021x2 & Qn & Dd
{
Dd = VectorRoundAddAndNarrow(Qn,Qm,esize2021x2);
Expand Down Expand Up @@ -1814,6 +1814,86 @@ extImm: "#"^thv_c0811 is TMode=1 & thv_c0811 { tmp:1 = thv_c0811; export tmp; }
Qd = VectorHalvingSubtract(Qn,Qm,esize2021,udt);
}

#######
# VFMA VFMS VFNMA and VFNMS
#

@if defined(VFPv4)

:vfma^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=1 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=1 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = zext(Sd:2 f+ (Sn:2 f* Sm:2));
}

:vfma^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=2 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=2 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = Sd f+ (Sn f* Sm);
}

:vfma^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=3 & c0606=0 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=3 & thv_c0606=0 & thv_c0404=0)) & Dm & Dn & Dd
{
Dd = Dd f+ (Dn f* Dm);
}

:vfms^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=1 & c0606=1 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=1 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = zext(Sd:2 f+ ((f- Sn:2) f* Sm:2));
}

:vfms^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=2 & c0606=1 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=2 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = Sd f+ ((f- Sn) f* Sm);
}

:vfms^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=2 & c1011=2 & c0809=3 & c0606=1 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=2 & thv_c1011=2 & thv_c0809=3 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd
{
Dd = Dd f+ ((f- Dn) f* Dm);
}

:vfnma^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=1 & c0606=1 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=1 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = zext((f- Sd:2) f+ ((f- Sn:2) f* Sm:2));
}

:vfnma^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=2 & c0606=1 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=2 & thv_c0606=1 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = (f- Sd) f+ ((f- Sn) f* Sm);
}

:vfnma^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=3 & c0606=1 & c0404=0) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=3 & thv_c0606=1 & thv_c0404=0)) & Dm & Dn & Dd
{
Dd = (f- Dd) f+ ((f- Dn) f* Dm);
}

:vfnms^COND^".f16" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=1 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=1 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = zext((f- Sd:2) f+ (Sn:2 f* Sm:2));
}

:vfnms^COND^".f32" Sd,Sn,Sm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=2 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=2 & thv_c0606=0 & thv_c0404=0)) & Sm & Sn & Sd
{
Sd = (f- Sd) f+ (Sn f* Sm);
}

:vfnms^COND^".f64" Dd,Dn,Dm is ( ( $(AMODE) & COND & c2327=0x1d & c2021=1 & c1011=2 & c0809=3 & c0606=0 & c0404=0 ) |
($(TMODE_E) & thv_c2327=0x1d & thv_c2021=1 & thv_c1011=2 & thv_c0809=3 & thv_c0606=0 & thv_c0404=0)) & Dm & Dn & Dd
{
Dd = (f- Dd) f+ (Dn f* Dm);
}

@endif # VFPv4

#######
# VLD1 (multiple single elements)
#
Expand Down
8 changes: 4 additions & 4 deletions src/Processors/ARM/data/languages/ARMv8.sinc
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Expand Up @@ -651,28 +651,28 @@ vcvt_56_128_dt: ".u32.f32"
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b100 & c0809=0b10)
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b10))
& COND & Sd & Sm
{ build COND; Sd = zext(round(Sm)); }
{ build COND; Sd = trunc(Sm); }

# F6.1.57 p3356 A1 opc2==101 && size==10 (c1618, c0809)
:vcvt^COND^".s32.f32" Sd,Sm
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b101 & c0809=0b10)
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b10))
& COND & Sd & Sm
{ build COND; Sd = sext(round(Sm)); }
{ build COND; Sd = trunc(Sm); }

# F6.1.57 p3356 A1 opc2==100 && size==11 (c1618, c0809)
:vcvt^COND^".u32.f64" Sd,Dm
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b100 & c0809=0b11)
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b100 & thv_c0809=0b11))
& COND & Sd & Dm
{ build COND; local tmp:8 = zext(round(Dm)); Sd = tmp:4; }
{ build COND; local tmp:8 = trunc(Dm); Sd = tmp:4; }

# F6.1.57 p3356 A1 opc2==101 && size==11 (c1618, c0809)
:vcvt^COND^".s32.f64" Sd,Dm
is ((TMode=0 & ARMcond=1 & c2327=0b11101 & c1921=0b111 & c1011=0b10 & c0607=0b11 & c0404=0 & c1618=0b101 & c0809=0b11)
| (TMode=1 & thv_c2831=0b1110 & thv_c2327=0b11101 & thv_c1921=0b111 & thv_c1011=0b10 & thv_c0607=0b11 & thv_c0404=0 & thv_c1618=0b101 & thv_c0809=0b11))
& COND & Sd & Dm
{ build COND; local tmp:8 = sext(round(Dm)); Sd = tmp:4; }
{ build COND; local tmp:8 = trunc(Dm); Sd = tmp:4; }

# The rounding mode depends on c0707=0 => FPSCR else ZERO

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2 changes: 1 addition & 1 deletion src/Processors/Atmel/data/languages/avr32a.pspec
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Expand Up @@ -2,7 +2,7 @@

<processor_spec>
<properties>
<property key="assemblyRating:avr32:BE:32:default" value="BRONZE"/>
<property key="assemblyRating:avr32:BE:32:default" value="PLATINUM"/>
</properties>
<programcounter register="PC"/>
</processor_spec>
11 changes: 8 additions & 3 deletions src/Processors/Atmel/data/languages/avr32a_arithmetic_operations.sinc
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Expand Up @@ -63,7 +63,8 @@ macro acrflags(OP1, tmpC, RES) {
# 010 1110 00100 dddd (Opcode Form)
# 0101 1100 0100 dddd (Byte half Form)
:ABS rd0 is rd0 & op13_3=0x2 & op9_4=0xe & op4_5=0x4 {
rd0 = abs(rd0);
local ztst:1 = rd0 s< 0;
rd0 = (zext(!ztst)*rd0) + (zext(ztst)*(-rd0));
ZSTATUS(rd0);
}

Expand Down Expand Up @@ -193,13 +194,17 @@ macro acrflags(OP1, tmpC, RES) {

:ADDABS erd0, RX9A, RY0A is (op13_3=7 & op4_5=0 & RX9A & RY0A; eop4_12=0xe4 & erd0)
{
erd0 = RX9A + abs(RY0A);
local ztst:1 = RY0A s< 0;
local ary0:4 = (zext(!ztst)*RY0A) + (zext(ztst)*(-RY0A));
erd0 = RX9A + ary0;
ZSTATUS(erd0);
}

:ADDABS erd0, RX9A, RY0A is (op13_3=7 & op4_5=0 & RX9A & RY0A; eop4_12=0xe4 & erd0 & erd0=0xf)
{
PC = RX9A + abs(RY0A);
local ztst:1 = RY0A s< 0;
local ary0:4 = (zext(!ztst)*RY0A) + (zext(ztst)*(-RY0A));
PC = RX9A + ary0;
ZSTATUS(PC);
goto [PC];
}
Expand Down
2 changes: 1 addition & 1 deletion src/Processors/JVM/data/languages/JVM.ldefs
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Expand Up @@ -5,7 +5,7 @@
endian="big"
size="32"
variant="default"
version="1.0"
version="1.1"
slafile="JVM.sla"
processorspec="JVM.pspec"
manualindexfile="../manuals/JVM.idx"
Expand Down
55 changes: 25 additions & 30 deletions src/Processors/JVM/data/languages/JVM.slaspec
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Expand Up @@ -1721,19 +1721,18 @@ Default:"default" addr is defaultbyte1; defaultbyte2; defaultbyte3; defaultbyte4
# lookupswitch
##################################################################################################

LookupSwitch_match:match _offset is matchbyte1; matchbyte2; matchbyte3; matchbyte4; offsetbyte1; offsetbyte2; offsetbyte3; offsetbyte4 [match = (matchbyte1 << 24) | (matchbyte2 << 16) | (matchbyte3 << 8) | (matchbyte4); _offset = (offsetbyte1 << 24) | (offsetbyte2 << 16) | (offsetbyte3 << 8) | (offsetbyte4); ]
#compute and display one match,offset pair
LookupSwitch_match:match _offset is matchbyte1; matchbyte2; matchbyte3; matchbyte4; offsetbyte1; offsetbyte2; offsetbyte3; offsetbyte4 [match = (matchbyte1 << 24) | (matchbyte2 << 16) | (matchbyte3 << 8) | (matchbyte4); _offset = inst_start + ((offsetbyte1 << 24) | (offsetbyte2 << 16) | (offsetbyte3 << 8) | (offsetbyte4)); ]
{
}

LookupSwitch_case:"lscase" lscase is (in_lookup_switch=1 & in_table_switch=0) [ lscase = switch_num; switch_num = switch_num - 1;]
#consume one match,offset pair and decrement the switch number
:^LookupSwitch_match, instruction is (in_lookup_switch=1 & in_table_switch=0); LookupSwitch_match; instruction [switch_num = switch_num - 1;]
{
}

:^LookupSwitch_case LookupSwitch_match, instruction is (in_lookup_switch=1 & in_table_switch=0); LookupSwitch_case; LookupSwitch_match; instruction
{
}

:"lscase" lscase LookupSwitch_match is (in_lookup_switch=1 & switch_num=1 & in_table_switch=0); LookupSwitch_match [in_lookup_switch=0; lscase=switch_num; ]
#leave the switch statement
:""LookupSwitch_match is (in_lookup_switch=1 & switch_num=1 & in_table_switch=0); LookupSwitch_match [in_lookup_switch=0;]
{
}

Expand All @@ -1744,14 +1743,14 @@ padSwitch: "" is alignmentPad = 2 & padVal & op ; pad1; pad2 { export *[const]:
padSwitch: "" is alignmentPad = 1 & padVal & op ; pad1 { export *[const]:1 padVal; }
padSwitch: "" is alignmentPad = 0 & padVal & op { export *[const]:1 padVal; }

dolookupswitch: _default, npairs is alignmentPad & defaultbyte1; defaultbyte2; defaultbyte3; defaultbyte4; npairsbyte1; npairsbyte2; npairsbyte3; npairsbyte4 [ npairs = (npairsbyte1 << 24) | (npairsbyte2 << 16) | (npairsbyte3 << 8) | npairsbyte4; _default = (defaultbyte1 << 24) | (defaultbyte2 << 16) | (defaultbyte3 << 8) | (defaultbyte4); switch_num = npairs; in_lookup_switch = 1;]
#Note: "Default" constructor does not play nice with switchAssist injection...
dolookupswitch: _default, npairs is alignmentPad & defaultbyte1; defaultbyte2; defaultbyte3; defaultbyte4; npairsbyte1; npairsbyte2; npairsbyte3; npairsbyte4 [ npairs = (npairsbyte1 << 24) | (npairsbyte2 << 16) | (npairsbyte3 << 8) | npairsbyte4; _default = inst_start + ((defaultbyte1 << 24) | (defaultbyte2 << 16) | (defaultbyte3 << 8) | defaultbyte4); switch_num = npairs; in_lookup_switch = 1;]
{
_padding:1 = alignmentPad;
_opcodeAddr:$(SIZE) = inst_start;
_defaultAddr:$(SIZE) = inst_start + _default;
_key:$(SIZE) = 0;
local _padding:1 = alignmentPad;
local _opcodeAddr:$(SIZE) = inst_start;
local _key:$(SIZE) = 0;
pop(_key);
_address:$(SIZE) = switchAssist(_key,_opcodeAddr,_padding,_defaultAddr,npairs:$(SIZE));
local _address:$(SIZE) = switchAssist(_key,_opcodeAddr,_padding,_default:$(SIZE),npairs:$(SIZE));
goto [ _address ];
}

Expand Down Expand Up @@ -2013,20 +2012,29 @@ _value :$(DOUBLE_SIZE) = 0;
# tableswitch
########################################################################################################################

#compute and display one switch offset
Switch_offset:_offset is offsetbyte1; offsetbyte2; offsetbyte3; offsetbyte4 [ _offset = inst_start + ((offsetbyte1<<24) | (offsetbyte2<<16) | (offsetbyte3<<8) | offsetbyte4); ]
{
}

Switch_case:"case" case is (in_table_switch=1) [ case = switch_high-switch_num; switch_num=switch_num-1; ]
# Switch entry that's not the last one.
# no pcode def - this construction is just for consuming all of the bytes of a tableswitch instructions
# decrements the switch number
:^Switch_offset, instruction is (in_table_switch=1 & in_lookup_switch=0); Switch_offset; instruction [switch_num = switch_num - 1;]
{
}

#Last switch entry. Get out of switch context.
:""Switch_offset is (in_table_switch=1 & in_lookup_switch=0 &switch_num=0); Switch_offset [ in_table_switch=0; ]
{
}

dotableswitch: Default, low, high is alignmentPad & Default;lowbyte1; lowbyte2; lowbyte3; lowbyte4; highbyte1; highbyte2; highbyte3; highbyte4 [ low = (lowbyte1 << 24) | (lowbyte2 << 16) | (lowbyte3 << 8) | lowbyte4; high = (highbyte1 << 24) | (highbyte2 << 16) | (highbyte3 << 8) | highbyte4; switch_low = low; switch_num = high - low; switch_high = high; in_table_switch = 1; ]

{
_offset :$(SIZE) = 0;
idx :$(SIZE) = 0;
padding:$(SIZE) = alignmentPad;
local _offset :$(SIZE) = 0;
local idx :$(SIZE) = 0;
local padding:$(SIZE) = alignmentPad;

pop(idx);
if (idx s< low) goto Default;
Expand All @@ -2037,7 +2045,6 @@ dotableswitch: Default, low, high is alignmentPad & Default;lowbyte1; lowbyte2;
goto [switch_target];
}


:tableswitch dotableswitch, instruction is in_table_switch=0 & in_lookup_switch=0 & op=0xaa & alignmentPad=0; dotableswitch; instruction
{
build dotableswitch;
Expand All @@ -2055,18 +2062,6 @@ dotableswitch: Default, low, high is alignmentPad & Default;lowbyte1; lowbyte2;
build dotableswitch;
}

# Switch entry that's not the last one.
# no pcode def - this construction is just for consuming all of the bytes of a tableswitch instructions
# decrements the switch number
:^Switch_case Switch_offset, instruction is (in_table_switch=1 & in_lookup_switch=0); Switch_case; Switch_offset; instruction
{
}

#Last switch entry. Get out of switch context.
:"case" case Switch_offset is (in_table_switch=1 & in_lookup_switch=0 &switch_num=0); Switch_offset [ in_table_switch=0; case=switch_high-switch_num; ]
{
}

#wide loads
:wide_iload index is (in_table_switch=0 & in_lookup_switch=0 & w_op=0xc415); indexbyte1; indexbyte2 [index = (indexbyte1 << 8) | indexbyte2; ]
{
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