Fix "call" pseudo instruction that uselessly modified register "t1"

[pacalet]

The assembler translates call label as a auipc / jalr pair:

auipc x6,imm1
jalr  x1,x6,imm2

It uses register x6 (t1) to do so while register x1 (ra) is available and must indeed be modified anyway to store the return address. Although the ILP32 Application Binary Interface (ABI) and other ABIs consider x6 as non-saved, I do not see any reason to enforce an ABI in RARS more than strictly needed. So, I suggest to translate call label as:

auipc x1,imm1
jalr  x1,x1,imm2

Note: one could claim that this is still ABI-related because we use x1 (ra). But using a register is unavoidable if one wants a call pseudo-instruction. Choosing x1 makes sense as it is the preferred register for this purpose in ILP32 and alike.

Note: another pseudo-instruction (and only one) also silently modifies a non-saved register: tail label. As its target register is x0 we cannot fix it as we did for call. My intuition is that tail shall be removed completely but this breaks backward compatibility. We should maybe add a warning in its brief description?

[github-actions]

Test Results

12 files  ±0  12 suites  ±0   37s ⏱️ +2s
 8 tests ±0   8 ✅ ±0  0 💤 ±0  0 ❌ ±0 
24 runs  ±0  24 ✅ ±0  0 💤 ±0  0 ❌ ±0 

Results for commit cb37651. ± Comparison against base commit 11f9a9e.

[privat]

What you propose is in fact conform to the standard and what GNU as does
https://github.com/riscv-non-isa/riscv-asm-manual/blob/39a23b69dded402bb41061deb1ae44efe99b80d1/src/asm-manual.adoc#L71

tail could keep using t1, but people, including students, that use tail should be advanced enough to understand the t1 surprise :)