PCI: rcar: Fix missing MACCTLR register setting in initialization seq…

…uence

The R-Car Gen2/3 manual - available at:

https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg1m.html#documents

"RZ/G Series User's Manual: Hardware" section

strictly enforces the MACCTLR initialization value - 39.3.1 - "Initial
Setting of PCI Express":

"Be sure to write the initial value (= H'80FF 0000) to MACCTLR before
enabling PCIETCTLR.CFINIT".

To avoid unexpected behavior and to match the SW initialization sequence
guidelines, this patch programs the MACCTLR with the correct value.

Note that the MACCTLR.SPCHG bit in the MACCTLR register description
reports that "Only writing 1 is valid and writing 0 is invalid" but this
"invalid" has to be interpreted as a write-ignore aka "ignored", not
"prohibited".

In Renesas Linux BSP, PM noirq resume function needs to initialize the
rcar-pcie register to call the read function of pci_ops from pci framework.
As a result, rcar_pcie_config_access() is called by rcar_pcie_read_conf().
Thus, there is PCIe link initialization in rcar_pcie_config_access() during
system resume.

Reported-by: Eugeniu Rosca <[email protected]>
Fixes: c25da47 ("PCI: rcar: Add Renesas R-Car PCIe driver")
Fixes: be20bbc ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()")
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Cc: <[email protected]> # v5.2+
(cherry picked from commit 7c7e53e)
[hoang vo: update commit log]
Signed-off-by: Hoang Vo <[email protected]>

drivers/pci/host/pcie-rcar.c

@@ -94,8 +94,11 @@
 #define  LINK_SPEED_2_5GTS	(1 << 16)
 #define  LINK_SPEED_5_0GTS	(2 << 16)
 #define MACCTLR			0x011058
+#define  MACCTLR_NFTS_MASK	GENMASK(23, 16)	/* The name is from SH7786 */
 #define  SPEED_CHANGE		BIT(24)
 #define  SCRAMBLE_DISABLE	BIT(27)
+#define  LTSMDIS		BIT(31)
+#define  MACCTLR_INIT_VAL	(LTSMDIS | MACCTLR_NFTS_MASK)
 #define PMSR			0x01105c
 #define  L1FAEG			BIT(31)
 #define  PM_ENTER_L1RX		BIT(23)
@@ -255,6 +258,7 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie,
 	if (val == 0 || (rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) {
 		/* Wait PCI Express link is re-initialized */
 		dev_info(&bus->dev, "Wait PCI Express link is re-initialized\n");
+		rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
 		rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
 		ret = rcar_pcie_wait_for_dl(pcie);
 		if (ret)
@@ -681,6 +685,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
 	if (IS_ENABLED(CONFIG_PCI_MSI))
 		rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
 
+	rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
+
 	/* Finish initialization - establish a PCI Express link */
 	rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);