Merge remote-tracking branch 'dev/3.19.0/rz' into 3.19.0/rz

core/arch/arm/plat-rz/common/drivers/r_sce/README.md

@@ -14,6 +14,7 @@ The SCE Driver is software for controlling SCE, which is the security IP of RZ M
 ### 1.1. Requirements
 
   - RZ Secure Crypto Engine library 1.0.0 (libr_secure_ip_1_0.a.1.0.0)
+  - RZ/V2H Secure Crypto Engine library 1.0.0 (libr_secure_ip_2_0.a.1.0.0)
 
 ### 1.2. Notice
 
@@ -30,7 +31,7 @@ The following table shows the document related to this function.
 | Number | Issuer  | Title                                                          | Edition           |
 |--------|---------|----------------------------------------------------------------|-------------------|
 | 1      | Renesas | RZ/G2L Security Manual                                         | Rev.1.00 or later |
-
+| 2      | Renesas | RZ/V2H Security Manual                                         | Rev.1.00 or later |
 
 ## 2. Driver Specifications
 
@@ -44,3 +45,6 @@ Describe the revision history of RZ MPU SCE Driver.
 
 - First release.
 
+### 3.2. v1.01
+
+- Support RZ/V2H EVK Board.

core/arch/arm/plat-rz/common/drivers/r_sce/doc/RZ_SCE_Driver_Usage.rst

@@ -54,7 +54,7 @@ The following table lists the hardware needed to use this utility.
 .. csv-table:: Hardware environment
     :header: "Name", "Note"
 
-    Target board,"RZ/G2L Device"
+    Target board,"RZ/G2L Device" and "RZ/V2H Device"
 
 -------------------------------------------------------
 1.4.1.Software Environment
@@ -65,7 +65,7 @@ This driver are designed for use with generic (or no specific) operating systems
 1.5.Requirement
 *************************************************************************
 
- - RZ Secure Crypto Engine library 1.0.0
+ - RZ Secure Crypto Engine library
 
 *************************************************************************
 1.6.Notice

core/arch/arm/plat-rz/common/drivers/r_sce/sub.mk

@@ -10,4 +10,6 @@ global-incdirs-y += inc/instances
 
 ifeq ($(CFG_PLATFORM_GROUP_g2l),y)
 ldflags-external += $(CFG_RZ_SCE_LIB_DIR)/libr_secure_ip_1_0.a.1.0.0
+else ifeq ($(CFG_PLATFORM_GROUP_v2h),y)
+ldflags-external += $(CFG_RZ_SCE_LIB_DIR)/libr_secure_ip_2_0.a.1.0.0
 endif

core/arch/arm/plat-rz/common/sub.mk

@@ -1,5 +1,5 @@
 srcs-$(CFG_RZ_HUK) += huk.c
-srcs-$(CFG_RZ_TSIP) += hw_rng.c
+srcs-$(CFG_RZ_TSIP) += hw_rng_tsip.c
 srcs-$(CFG_RZ_RSIP) += hw_rng_rsip.c
 
 subdirs-y += drivers

core/arch/arm/plat-rz/conf.mk

@@ -27,6 +27,9 @@ include core/arch/arm/plat-rz/g3s/rzg3s_conf.mk
 else ifeq ($(PLATFORM_FLAVOR),g3s_dev14_1)
 $(call force,CFG_PLATFORM_GROUP_g3s,y)
 include core/arch/arm/plat-rz/g3s/rzg3s_conf.mk
+else ifeq ($(PLATFORM_FLAVOR),v2h_evk_1)
+$(call force,CFG_PLATFORM_GROUP_v2h,y)
+include core/arch/arm/plat-rz/v2h/rzv2h_conf.mk
 else
 $(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
 endif

core/arch/arm/plat-rz/platform_config.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 /*
- * Copyright (c) 2021, Renesas Electronics
+ * Copyright (c) 2021-2024, Renesas Electronics
  */
 
 #ifndef PLATFORM_CONFIG_H
@@ -10,6 +10,8 @@
 #include "g2l/rzg2l_config.h"
 #elif defined(CFG_PLATFORM_GROUP_g3s)
 #include "g3s/rzg3s_config.h"
+#elif defined(CFG_PLATFORM_GROUP_v2h)
+#include "v2h/rzv2h_config.h"
 #endif
 
 #endif /*PLATFORM_CONFIG_H*/

core/arch/arm/plat-rz/sub.mk

@@ -2,5 +2,6 @@ global-incdirs-y += .
 
 subdirs-$(CFG_PLATFORM_GROUP_g2l) += g2l
 subdirs-$(CFG_PLATFORM_GROUP_g3s) += g3s
+subdirs-$(CFG_PLATFORM_GROUP_v2h) += v2h
 
 subdirs-y += common

core/arch/arm/plat-rz/v2h/drivers/cpg/cpg.c

@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2024, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <stdint.h>
+#include <stddef.h>
+#include <assert.h>
+#include <io.h>
+#include <initcall.h>
+#include <mm/core_memprot.h>
+#include <platform_config.h>
+#include <cpg.h>
+#include <cpg_regs.h>
+
+#define CPG_T_CLK						(0)
+#define CPG_T_RST						(1)
+
+typedef struct {
+	uintptr_t addr;
+	uint32_t  val;
+} CPG_REG_SETTING;
+
+typedef struct {
+	CPG_REG_SETTING reg;
+	CPG_REG_SETTING mon;
+	uint32_t  type;
+} CPG_SETUP_DATA;
+
+
+register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CPG_REG_BASE, CPG_REG_SIZE);
+
+static vaddr_t cpg_base;
+
+inline static void cpg_io_write(uint32_t reg, uint32_t data)
+{
+	DMSG("cpg_io_write: Addr:0x%x, Val:0x%x ", reg, data);
+	io_write32(cpg_base + reg, data);
+}
+
+inline static uint32_t cpg_io_read(uint32_t reg)
+{
+	uint32_t ret;
+	ret = io_read32(cpg_base + reg);
+	DMSG("cpg_io_read: Addr:0x%x, Val:0x%x ", reg, ret);
+	return ret;
+}
+
+static CPG_SETUP_DATA cpg_clk_on_tbl[] = {
+
+	{	/* xSPI */
+		.reg =  {
+				.addr = (uintptr_t)CPG_CLKON_9,
+				.val  = 0x00008000,
+				},
+
+		.mon =  {
+				.addr = (uintptr_t)CPG_CLKMON_4,
+				.val  = 0x80000000,
+				},
+
+		.type = CPG_T_CLK
+	},
+
+	{	/* xSPI */
+		.reg =  {
+				.addr = (uintptr_t)CPG_CLKON_10,
+				.val  = 0x00000003,
+				},
+
+		.mon =  {
+				.addr = (uintptr_t)CPG_CLKMON_5,
+				.val  = 0x00000007,
+				},
+
+		.type = CPG_T_CLK
+	},
+};
+
+
+static CPG_SETUP_DATA cpg_reset_tbl[] = {
+	{	/* xSPI */
+		.reg =  {
+				.addr = (uintptr_t)CPG_RST_10,
+				.val  = 0x00000018,
+				},
+
+		.mon =  {
+				.addr = (uintptr_t)CPG_RSTMON_4,
+				.val  = 0x00300000,
+				},
+
+		.type = CPG_T_RST
+	}
+};
+
+static void cpg_clkon_rst(CPG_SETUP_DATA const *array, uint32_t num)
+{
+	int i;
+	uint32_t mask;
+	uint32_t cmp;
+
+	for (i = 0; i < num; i++, array++) {
+		/*
+		 * Upper 16bits are enables for lower 16bits so write the upper 16bits with same value as lower value
+		 */
+		uint32_t val = (array->reg.val & 0xFFFF) | ((array->reg.val & 0xFFFF) << 16);
+
+		cpg_io_write(array->reg.addr, val);
+
+		mask = array->mon.val;
+		cmp  = mask;
+
+		if (array->type == CPG_T_RST)
+			cmp = ~cmp;
+
+		while ((cpg_io_read(array->mon.addr) & mask) != (cmp & mask))
+			;
+	}
+}
+
+static void cpg_clkoff_rst(CPG_SETUP_DATA const *array, uint32_t num)
+{
+	int i;
+	uint32_t mask;
+	uint32_t cmp;
+
+	for (i = 0; i < num; i++, array++) {
+		/*
+		 * Upper 16bits are enables for lower 16bits so write the upper 16bits with same value as lower value
+		 */
+		uint32_t val = (array->reg.val & 0xFFFF) | ((array->reg.val & 0xFFFF) << 16);
+
+
+		if ((array->type == CPG_T_CLK) || (array->type == CPG_T_RST))
+			val = val & 0xffff0000;
+
+		cpg_io_write(array->reg.addr, val);
+
+		mask = array->mon.val;
+		cmp  = mask;
+
+		if (array->type == CPG_T_CLK)
+			cmp = ~cmp;
+
+		while ((cpg_io_read(array->mon.addr) & mask) != (cmp & mask))
+			;
+	}
+}
+
+
+
+void cpg_xspi_start(void)
+{
+	DMSG("cpg_xspi_start is called.");
+
+
+	cpg_clkon_rst(&cpg_clk_on_tbl[0], ARRAY_SIZE(cpg_clk_on_tbl));
+	cpg_clkon_rst(&cpg_reset_tbl[0], ARRAY_SIZE(cpg_reset_tbl));
+
+	cpg_io_write(CPG_BUS_4_MSTOP, 0x00200000);
+	cpg_io_write(CPG_BUS_5_MSTOP, 0x00200000);
+
+}
+
+void cpg_xspi_stop(void)
+{
+	DMSG("cpg_xspi_stop is called.");
+
+	cpg_clkoff_rst(&cpg_clk_on_tbl[0], ARRAY_SIZE(cpg_clk_on_tbl));
+	cpg_clkoff_rst(&cpg_reset_tbl[0], ARRAY_SIZE(cpg_reset_tbl));
+
+	cpg_io_write(CPG_BUS_4_MSTOP, 0x00200020);
+	cpg_io_write(CPG_BUS_5_MSTOP, 0x00200020);
+}
+
+static TEE_Result cpg_init(void)
+{
+	cpg_base = (vaddr_t)phys_to_virt_io(CPG_REG_BASE, CPG_REG_SIZE);
+
+	return TEE_SUCCESS;
+}
+
+driver_init(cpg_init);

core/arch/arm/plat-rz/v2h/drivers/cpg/cpg.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CPG_H_
+#define _CPG_H_
+
+extern void cpg_xspi_start(void);
+extern void cpg_xspi_stop(void);
+
+#endif /* _CPG_H_ */

core/arch/arm/plat-rz/v2h/drivers/cpg/cpg_regs.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __CPG_REGS_H__
+#define __CPG_REGS_H__
+
+#define CPG_CLKON_9								(0x0624)	/* CGC Control Register xSPI */
+#define CPG_CLKON_10							(0x0628)	/* CGC Control Register xSPI */
+
+#define CPG_CLKMON_4							(0x0810)	/* CGC Monitor Register xSPI */
+#define CPG_CLKMON_5							(0x0814)	/* CGC Monitor Register xSPI */
+
+
+#define CPG_BUS_4_MSTOP							(0x0D0C)	/* MSTOP register 4 */
+#define CPG_BUS_5_MSTOP							(0x0D10)	/* MSTOP register 5 */
+#define CPG_RST_10								(0x0928)	/* Reset Control Register xSPI */
+#define CPG_RSTMON_4							(0x0A10)	/* Reset Monitor Registers xSPI */
+
+#endif	/* __CPG_REGS_H__ */

core/arch/arm/plat-rz/v2h/drivers/cpg/sub.mk

@@ -0,0 +1,3 @@
+global-incdirs-y += .
+
+srcs-y += cpg.c