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Draft: Add m-mode, s-mode CLIC interrupt testcases #436

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Draft: Add m-mode, s-mode CLIC interrupt testcases #436

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Commits on Jun 6, 2024

  1. Draft: Add m-mode CLIC interrupt testcases 

    This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic


Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers @jamesbeyond
    dansmathers authored and jamesbeyond committed Jun 6, 2024
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  2. Draft: Add m-mode CLIC interrupt testcases 

    This is a draft version of the m-mode (Smclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note, pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic

Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers @jamesbeyond
    dansmathers authored and jamesbeyond committed Jun 6, 2024
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    09cb8de View commit details
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  3. Draft: Add s-mode CLIC interrupt testcases 

    his is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers @jamesbeyond
    dansmathers authored and jamesbeyond committed Jun 6, 2024
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    Copy the full SHA
    68e9b39 View commit details
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  4. Draft: Add s-mode CLIC interrupt testcases 

    This is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers @jamesbeyond
    dansmathers authored and jamesbeyond committed Jun 6, 2024
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    Copy the full SHA
    35ee9c1 View commit details
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  5. Draft: Add m/s-mode CLIC interrupt testcases 

    This is a draft version of the m-mode (Smclic), s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Smclic

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers @jamesbeyond
    dansmathers authored and jamesbeyond committed Jun 6, 2024
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    2e3b80b View commit details
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  6. increased size of signature region, normalized nxti checking 

    to allow different elf files between dut and ref, compare xnxti value to xtvt value
increased size of signature region. 32 was too small.

Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers @jamesbeyond
    dansmathers authored and jamesbeyond committed Jun 6, 2024
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  7. normalized nxti checking 

    to allow comparison between compiles at different code locations, xnxti signature value is compared to xtvt value.

Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers @jamesbeyond
    dansmathers authored and jamesbeyond committed Jun 6, 2024
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  8. adding shv testcases 

    Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers @jamesbeyond
    dansmathers authored and jamesbeyond committed Jun 6, 2024
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  9. clicshv tests - draft. 

    Signed-off-by: Dan Smathers <[email protected]>
    @dansmathers @jamesbeyond
    dansmathers authored and jamesbeyond committed Jun 6, 2024
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