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robehn committed Dec 20, 2024
1 parent cf28fd4 commit 5b405e5
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Showing 4 changed files with 94 additions and 1 deletion.
18 changes: 18 additions & 0 deletions make/autoconf/flags-cflags.m4
Original file line number Diff line number Diff line change
Expand Up @@ -916,6 +916,24 @@ AC_DEFUN([FLAGS_SETUP_CFLAGS_CPU_DEP],
fi
fi
AC_SUBST($2SVE_CFLAGS)
if test "x$OPENJDK_TARGET_CPU" = "xriscv64"; then
AC_MSG_CHECKING([if RVV/vector sigcontext supported])
AC_COMPILE_IFELSE([AC_LANG_PROGRAM([#include <linux/ptrace.h>],
[
return (int)sizeof(struct __riscv_v_ext_state);
])],
[
AC_MSG_RESULT([yes])
$2RVV_CFLAGS=""
],
[
AC_MSG_RESULT([no])
$2RVV_CFLAGS="-DNO_RVV_SIGCONTEXT"
]
)
fi
AC_SUBST($2RVV_CFLAGS)
])

AC_DEFUN_ONCE([FLAGS_SETUP_BRANCH_PROTECTION],
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3 changes: 3 additions & 0 deletions make/autoconf/spec.gmk.template
Original file line number Diff line number Diff line change
Expand Up @@ -831,6 +831,9 @@ OS_VERSION_MICRO := @OS_VERSION_MICRO@
# Arm SVE
SVE_CFLAGS := @SVE_CFLAGS@

# Riscv RVV
RVV_CFLAGS := @RVV_CFLAGS@

# Images directory definitions
JDK_IMAGE_SUBDIR := jdk
JRE_IMAGE_SUBDIR := jre
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4 changes: 4 additions & 0 deletions make/hotspot/lib/CompileJvm.gmk
Original file line number Diff line number Diff line change
Expand Up @@ -135,6 +135,10 @@ else ifeq ($(call isTargetCpu, x86_64), true)
JVM_EXCLUDE_PATTERNS += x86_32
endif

ifeq ($(call isTargetCpu, riscv64), true)
JVM_CFLAGS += $(RVV_CFLAGS)
endif

JVM_OPTIMIZATION ?= HIGHEST_JVM

# Need to set JVM_STRIPFLAGS to the default value from SPEC since the STRIPFLAGS
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70 changes: 69 additions & 1 deletion src/hotspot/os_cpu/linux_riscv/os_linux_riscv.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -56,8 +56,9 @@

// put OS-includes here
# include <dlfcn.h>
# include <fpu_control.h>
# include <errno.h>
# include <fpu_control.h>
# include <linux/ptrace.h>
# include <pthread.h>
# include <signal.h>
# include <stdio.h>
Expand Down Expand Up @@ -350,6 +351,73 @@ void os::print_context(outputStream *st, const void *context) {
st->print_cr("%-*.*s=" INTPTR_FORMAT, 8, 8, reg_abi_names[r], (uintptr_t)uc->uc_mcontext.__gregs[r]);
}
st->cr();
const struct __riscv_mc_d_ext_state * const f_ext_state = &(uc->uc_mcontext.__fpregs.__d);
st->print_cr("Floating point state:");
st->print_cr("fcsr=" UINT32_FORMAT, f_ext_state->__fcsr);
st->print_cr("Floating point registers:");
for (int r = 0; r < 32; r++) {
st->print_cr("f%d=" INTPTR_FORMAT " | %g", r, (intptr_t)f_ext_state->__f[r], (double)f_ext_state->__f[r]);
}
st->cr();

#ifdef NO_RVV_SIGCONTEXT
st->print_cr("Vector state: JVM compiled without vector sigcontext support");
#else
// This magic number is not in any user-space header.
// No other choice but to define it.
#ifndef RISCV_V_MAGIC
#define RISCV_V_MAGIC 0x53465457
#endif

// vector state
struct __riscv_extra_ext_header *ext;
struct __riscv_v_ext_state *v_ext_state;

// Find the vector context
ext = (struct __riscv_extra_ext_header *)(&uc->uc_mcontext.__fpregs);
if (ext->hdr.magic != RISCV_V_MAGIC) {
st->print_cr("Vector state: not found");
return;
}

// size = sizeof(struct __riscv_ctx_hdr) + sizeof(struct __sc_riscv_v_state) + riscv_v_vsize;
uint32_t ext_size = ext->hdr.size;

if (ext_size < (sizeof(struct __riscv_ctx_hdr) + sizeof(*v_ext_state))) {
st->print_cr("Vector state: not found, invalid size");
return;
}

ext_size -= (sizeof(struct __riscv_ctx_hdr) + sizeof(*v_ext_state));

v_ext_state = (struct __riscv_v_ext_state *)((char *)(ext) + sizeof(*ext));

st->print_cr("Vector state:");
st->print_cr("vstart=" INTPTR_FORMAT, v_ext_state->vstart);
st->print_cr("vl=" INTPTR_FORMAT, v_ext_state->vl);
st->print_cr("vtype=" INTPTR_FORMAT, v_ext_state->vtype);
st->print_cr("vcsr=" INTPTR_FORMAT, v_ext_state->vcsr);
st->print_cr("vlenb=" INTPTR_FORMAT, v_ext_state->vlenb);
st->print_cr("Vector registers:");

uint64_t vr_size = v_ext_state->vlenb;

if (ext_size < (32 * vr_size)) {
st->print_cr("Vector registers: not found, invalid size");
return;
}
// datap format is undocumented, but is generated by kernel function riscv_v_vstate_save().
uint8_t *regp = (uint8_t *)v_ext_state->datap;
for (int r = 0; r < 32; r++) {
st->print("v%d=0x", r);
for (int i = vr_size; i > 0; i--) {
st->print("%02" PRIx8, regp[i-1]);
}
st->print_cr("");
regp += vr_size;
}
st->cr();
#endif
}

void os::print_register_info(outputStream *st, const void *context, int& continuation) {
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