clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set

Many qcom clock drivers do not have .width set. In that case value of
(p)->width - 1 will be negative which breaks clock tree. Fix this
by checking if width is zero, and pass 3 to GENMASK if that's the case.

Fixes: 1c35411 ("clk: qcom: support for 2 bit PLL post divider")
Fixes: 2c4553e ("clk: qcom: clk-alpha-pll: Fix the pll post div mask")
Signed-off-by: Barnabás Czémán <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>

drivers/clk/qcom/clk-alpha-pll.c

@@ -40,7 +40,7 @@
 
 #define PLL_USER_CTL(p)		((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
 # define PLL_POST_DIV_SHIFT	8
-# define PLL_POST_DIV_MASK(p)	GENMASK((p)->width - 1, 0)
+# define PLL_POST_DIV_MASK(p)	GENMASK((p)->width ? (p)->width - 1 : 3, 0)
 # define PLL_ALPHA_MSB		BIT(15)
 # define PLL_ALPHA_EN		BIT(24)
 # define PLL_ALPHA_MODE		BIT(25)