updated SSCI and VCIX RTL busDefinitions

specs/sifive.com/SSCI/0.1.0/SSCI_rtl.json5

@@ -0,0 +1,107 @@
+{
+  $schema: 'https://drom.io/duh.json',
+  abstractionDefinition: {
+    vendor: 'sifive.com', library: 'SSCI', name: 'SSCI', version: '0.1.0',
+    busType: {
+      vendor: 'sifive.com', library: 'SSCI', name: 'SSCI', version: '0.1.0'
+    },
+    ports: {
+      clock: {
+        description: 'Clock at same frequency as core clock',
+        wire: {
+          isClock: true,
+          onInitiator: { width: 1, direction: 'in', presence: 'required' },
+          onTarget:    { width: 1, direction: 'in', presence: 'required' }
+        }
+      },
+      reset: {
+        description: 'Synchronous reset signal, positive polarity',
+        wire: {
+          isReset: true,
+          onInitiator: { width: 1, direction: 'in', presence: 'required' },
+          onTarget:    { width: 1, direction: 'in', presence: 'required' }
+        }
+      },
+      req_valid: {
+        description: 'Processor is sending a valid command to the coprocessor',
+        wire: {
+          onInitiator: { width: 1, direction: 'out', presence: 'required' },
+          onTarget:    { width: 1, direction: 'in', presence: 'required' }
+        }
+      },
+      req_ready: {
+        description: 'Coprocessor can accept a new command',
+        wire: {
+          onInitiator: { width: 1, direction: 'in', presence: 'required' },
+          onTarget:    { width: 1, direction: 'out', presence: 'required' }
+        }
+      },
+      req_data1: {
+        description: 'Source operand 1',
+        wire: {
+          isData: true,
+          onInitiator: { width: 'XLEN', direction: 'out', presence: 'required' },
+          onTarget:    { width: 'XLEN', direction: 'in', presence: 'required' }
+        }
+      },
+      req_data2: {
+        description: 'Source operand 2',
+        wire: {
+          isData: true,
+          onInitiator: { width: 'XLEN', direction: 'out', presence: 'required' },
+          onTarget:    { width: 'XLEN', direction: 'in', presence: 'required' }
+        }
+      },
+      req_funct7: {
+        description: 'Instruction bits 31..25',
+        wire: {
+          onInitiator: { width: 7, direction: 'out', presence: 'required' },
+          onTarget:    { width: 7, direction: 'in', presence: 'required' }
+        }
+      },
+      req_funct3: {
+        description: 'Instruction bits 14..12',
+        wire: {
+          onInitiator: { width: 3, direction: 'out', presence: 'required' },
+          onTarget:    { width: 3, direction: 'in', presence: 'required' },
+        },
+      },
+      req_respond: {
+        description: 'Encodes if a response is required',
+        wire: {
+          onInitiator: { width: 1, direction: 'out', presence: 'required' },
+          onTarget:    { width: 1, direction: 'in', presence: 'required' },
+        },
+      },
+      resp_valid: {
+        description: 'Coprocessor is sending a valid response to the processor',
+        wire: {
+          onInitiator: { width: 1, direction: 'in', presence: 'required' },
+          onTarget:    { width: 1, direction: 'out', presence: 'required' },
+        },
+      },
+      resp_ready: {
+        description: 'Processor can accept a response',
+        wire: {
+          onInitiator: { width: 1, direction: 'out', presence: 'required' },
+          onTarget:    { width: 1, direction: 'in', presence: 'required' },
+        },
+      },
+      resp_data: {
+        description: 'Response data',
+        wire: {
+          isData: true,
+          onInitiator: { width: 'XLEN', direction: 'in', presence: 'required' },
+          onTarget:    { width: 'XLEN', direction: 'out', presence: 'required' }
+        }
+      }
+    },
+    props: {
+      XLEN: {
+        type: 'integer',
+        enum: [32, 64],
+        description: 'integer register width'
+      }
+    }
+  }
+}

specs/sifive.com/VCIX/1.0.0/VCIX_rtl.json5

@@ -0,0 +1,157 @@
+{
+  $schema: 'https://drom.io/duh.json',
+  abstractionDefinition: {
+    vendor: 'sifive.com', library: 'VCIX', name: 'VCIX_rtl', version: '1.0.0',
+    busType: {
+      vendor: 'sifive.com', library: 'VCIX', name: 'VCIX', version: '1.0.0'
+    },
+    ports: {
+      clock: {
+        description: 'Clock (same frequency as core clock).',
+        wire: {
+          isClock: true,
+          onInitiator: { width: 1, direction: 'in', presence: 'required' },
+          onTarget:    { width: 1, direction: 'in', presence: 'required' }
+        }
+      },
+      reset: {
+        description: 'Synchronous reset signal, positive polarity.',
+        wire: {
+          isReset: true,
+          onInitiator: { width: 1, direction: 'in', presence: 'required' },
+          onTarget:    { width: 1, direction: 'in', presence: 'required' }
+        }
+      },
+      req_valid: {
+        description: 'Processor is sending a valid command to the coprocessor.',
+        wire: {
+          onInitiator: { width: 1, direction: 'out', presence: 'required' },
+          onTarget:    { width: 1, direction: 'in', presence: 'required' }
+        }
+      },
+      req_ready: {
+        description: 'Coprocessor can accept a command.',
+        wire: {
+          onInitiator: { width: 1, direction: 'in', presence: 'required' },
+          onTarget:    { width: 1, direction: 'out', presence: 'required' }
+        },
+      },
+      req_data1: {
+        description: 'Source operand 1.',
+        wire: {
+          isData: true,
+          onInitiator: { width: 'DLEN', direction: 'out', presence: 'required' },
+          onTarget:    { width: 'DLEN', direction: 'in', presence: 'required' }
+        }
+      },
+      req_data2: {
+        description: 'Source operand 2.',
+        wire: {
+          isData: true,
+          onInitiator: { width: 'DLEN', direction: 'out', presence: 'required' },
+          onTarget:    { width: 'DLEN', direction: 'in', presence: 'required' }
+        }
+      },
+      req_data3: {
+        description: 'Source operand 3.',
+        wire: {
+          isData: true,
+          onInitiator: { width: '2 * DLEN', direction: 'out', presence: 'required' },
+          onTarget:    { width: '2 * DLEN', direction: 'in', presence: 'required' }
+        }
+      },
+      req_func6: {
+        description: 'Instruction bits 31..26.',
+        wire: {
+          onInitiator: { width: 6, direction: 'out', presence: 'required' },
+          onTarget:    { width: 6, direction: 'in', presence: 'required' }
+        }
+      },
+      req_vm: {
+        description: 'Instruction bit 25; when 1, indicates vd is not written.',
+        wire: {
+          onInitiator: { width: 1, direction: 'out', presence: 'required' },
+          onTarget:    { width: 1, direction: 'in', presence: 'required' }
+        }
+      },
+      req_rs2: {
+        description: 'Instruction bits 24..20 (rs2 field).',
+        wire: {
+          onInitiator: { width: 5, direction: 'out', presence: 'required' },
+          onTarget:    { width: 5, direction: 'in', presence: 'required' }
+        }
+      },
+      req_rs1: {
+        description: 'Instruction bits 19..15 (rs1 field).',
+        wire: {
+          onInitiator: { width: 5, direction: 'out', presence: 'required' },
+          onTarget:    { width: 5, direction: 'in', presence: 'required' }
+        }
+      },
+      req_funct3: {
+        description: 'Instruction bits 14..12.',
+        wire: {
+          onInitiator: { width: 3, direction: 'out', presence: 'required' },
+          onTarget:    { width: 3, direction: 'in', presence: 'required' }
+        }
+      },
+      req_rd: {
+        description: 'Instruction bits 11..7 (rd field).',
+        wire: {
+          onInitiator: { width: 5, direction: 'out', presence: 'required' },
+          onTarget:    { width: 5, direction: 'in', presence: 'required' }
+        }
+      },
+      req_vsew: {
+        description: 'Current setting of vtype.vsew (i.e., log2(SEW / 8)).',
+        wire: {
+          onInitiator: { width: 3, direction: 'out', presence: 'required' },
+          onTarget:    { width: 3, direction: 'in', presence: 'required' }
+        }
+      },
+      req_vlmul: {
+        description: 'Current setting of vtype.vlmul (i.e., log2(LMUL) as two\'s complement integer).',
+        wire: {
+          onInitiator: { width: 3, direction: 'out', presence: 'required' },
+          onTarget:    { width: 3, direction: 'in', presence: 'required' }
+        }
+      },
+      req_vl_in_bytes_minus_1: {
+        description: 'Current vector length setting, measured in bytes, minus one (i.e., VL * SEW / 8 - 1).',
+        wire: {
+          onInitiator: { width: 'log2(VLEN)', direction: 'out', presence: 'required' },
+          onTarget:    { width: 'log2(VLEN)', direction: 'in', presence: 'required' }
+        }
+      },
+      resp_valid: {
+        description: 'Coprocessor is sending a valid response to the processor.',
+        wire: {
+          onInitiator: { width: 1, direction: 'in', presence: 'required' },
+          onTarget:    { width: 1, direction: 'out', presence: 'required' }
+        }
+      },
+      resp_ready: {
+        description: 'Processor can accept a response.',
+        wire: {
+          onInitiator: { width: 1, direction: 'out', presence: 'required' },
+          onTarget:    { width: 1, direction: 'in', presence: 'required' }
+        }
+      },
+      resp_data: {
+        description: 'Response data.',
+        wire: {
+          isData: true,
+          onInitiator: { width: '2 * DLEN', direction: 'in', presence: 'required' },
+          onTarget:    { width: '2 * DLEN', direction: 'out', presence: 'required' }
+        }
+      }
+    },
+    props: {
+      DLEN: {
+        type: 'integer',
+        enum: [256, 512],
+        description: 'vector data length'
+      }
+    }
+  }
+}