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[next] Add support for L2 LIM/Prefetcher/Performance Monitor #572

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[next] Add support for L2 LIM/Prefetcher/Performance Monitor #572

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9937d49
Bump ldscript generator for L2 LIM
nategraff-sifive Oct 22, 2020
95804fc
Regen BSPs for L2 LIM linker scripts
nategraff-sifive Oct 22, 2020
6afe4fd
Add support for L2 prefetcher, LIM, and perf monitor
nategraff-sifive Oct 23, 2020
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9 changes: 9 additions & 0 deletions .gitmodules
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Original file line number Diff line number Diff line change
Expand Up @@ -145,3 +145,12 @@
[submodule "scl-metal"]
path = scl-metal
url = https://github.com/sifive/scl-metal.git
[submodule "software/lim"]
path = software/lim
url = https://github.com/sifive/example-lim.git
[submodule "software/example-l2pf"]
path = software/example-l2pf
url = https://github.com/sifive/example-l2pf.git
[submodule "software/example-l2pm"]
path = software/example-l2pm
url = https://github.com/sifive/example-l2pm.git
24 changes: 21 additions & 3 deletions bsp/freedom-e310-arty/metal.default.lds
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Expand Up @@ -24,6 +24,7 @@ PHDRS
ram PT_LOAD;
itim_init PT_LOAD;
text PT_LOAD;
lim_init PT_LOAD;
}

SECTIONS
Expand Down Expand Up @@ -159,7 +160,6 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)

} >rom :rom

/* ITIM SECTION
Expand All @@ -180,10 +180,28 @@ SECTIONS
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );

/* LIM SECTION
*
* The following sections contain data which is copied from read-only
* memory into a loosely integrated memory (LIM), which is shared with L2
* cache, during pre-main program initialization.
*
* Generally, the data copied into the LIM should be performance-critical
* functions which benefit from low instruction-fetch latency.
*/

.lim : ALIGN(8) {
*(.lim .lim.*)
} >ram AT>rom :lim_init

PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );

/* TEXT SECTION
*
* The following section contains the code of the program, excluding
* everything that's been allocated into the ITIM already
* everything that's been allocated into the ITIM/LIM already
*/

.text : {
Expand Down Expand Up @@ -260,7 +278,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
39 changes: 31 additions & 8 deletions bsp/freedom-e310-arty/metal.freertos.lds
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Expand Up @@ -27,6 +27,7 @@ PHDRS
ram PT_LOAD;
itim_init PT_LOAD;
text PT_LOAD;
lim_init PT_LOAD;
}

SECTIONS
Expand Down Expand Up @@ -132,15 +133,16 @@ SECTIONS
PROVIDE_HIDDEN ( metal_destructors_end = .);
} >rom :rom

.privileged_functions : ALIGN (4) {
.privileged_functions : ALIGN (32) {
__privileged_functions_start__ = .;
KEEP(*(privileged_functions))
. = ALIGN(4);
. = ALIGN(32);
__privileged_functions_end__ = .;
} >rom


.ctors : {
. = ALIGN(32);
__unprivileged_section_start__ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
Expand Down Expand Up @@ -169,8 +171,6 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
__unprivileged_section_end__ = .;

} >rom :rom

/* ITIM SECTION
Expand All @@ -191,17 +191,38 @@ SECTIONS
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );

/* LIM SECTION
*
* The following sections contain data which is copied from read-only
* memory into a loosely integrated memory (LIM), which is shared with L2
* cache, during pre-main program initialization.
*
* Generally, the data copied into the LIM should be performance-critical
* functions which benefit from low instruction-fetch latency.
*/

.lim : ALIGN(8) {
*(.lim .lim.*)
} >ram AT>rom :lim_init

PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );

/* TEXT SECTION
*
* The following section contains the code of the program, excluding
* everything that's been allocated into the ITIM already
* everything that's been allocated into the ITIM/LIM already
*/

.text : {
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
*(freertos_system_calls)
. = ALIGN(32);
__unprivileged_section_end__ = .;
} >rom :text

/* RAM SECTION
Expand All @@ -218,6 +239,7 @@ SECTIONS
*/

.data : ALIGN(8) {
. = ALIGN(32);
__unprivileged_data_section_start__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
Expand Down Expand Up @@ -257,19 +279,20 @@ SECTIONS
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(32);
__unprivileged_data_section_end__ = .;
} >ram :ram

PROVIDE( metal_segment_bss_source_start = LOADADDR(.tbss) );
PROVIDE( metal_segment_bss_target_start = ADDR(.tbss) );
PROVIDE( metal_segment_bss_target_end = ADDR(.bss) + SIZEOF(.bss) );

.privileged_data (NOLOAD) : ALIGN(8) {
.privileged_data (NOLOAD) : ALIGN(32) {
__privileged_data_start__ = .;
*(privileged_data)
/* Non kernel data is kept out of the first _Privileged_Data_Region_Size
bytes of SRAM. */
. = ALIGN(4);
. = ALIGN(32);
__privileged_data_end__ = .;
} >ram

Expand All @@ -281,7 +304,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
23 changes: 21 additions & 2 deletions bsp/freedom-e310-arty/metal.ramrodata.lds
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Expand Up @@ -28,6 +28,7 @@ PHDRS
ram PT_LOAD;
itim_init PT_LOAD;
text PT_LOAD;
lim_init PT_LOAD;
}

SECTIONS
Expand Down Expand Up @@ -172,10 +173,28 @@ SECTIONS
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );

/* LIM SECTION
*
* The following sections contain data which is copied from read-only
* memory into a loosely integrated memory (LIM), which is shared with L2
* cache, during pre-main program initialization.
*
* Generally, the data copied into the LIM should be performance-critical
* functions which benefit from low instruction-fetch latency.
*/

.lim : ALIGN(8) {
*(.lim .lim.*)
} >ram AT>rom :lim_init

PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );

/* TEXT SECTION
*
* The following section contains the code of the program, excluding
* everything that's been allocated into the ITIM already
* everything that's been allocated into the ITIM/LIM already
*/

.text : {
Expand Down Expand Up @@ -264,7 +283,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
32 changes: 21 additions & 11 deletions bsp/freedom-e310-arty/metal.scratchpad.lds
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Expand Up @@ -25,6 +25,7 @@ PHDRS
ram PT_LOAD;
itim_init PT_LOAD;
text PT_LOAD;
lim_init PT_LOAD;
}

SECTIONS
Expand Down Expand Up @@ -72,16 +73,8 @@ SECTIONS
* certain core features */
PROVIDE(__metal_chicken_bit = 1);

/* The memory_ecc_scrub bit is used by _entry code to enable/disable
* memories scrubbing to zero */
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
PROVIDE( metal_dtim_0_memory_start = 0x80000000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x4000 );
PROVIDE( metal_itim_0_memory_start = 0x8000000 );
PROVIDE( metal_itim_0_memory_end = 0x8000000 + 0x4000 );

/* ROM SECTION
*
* The following sections contain data which lives in read-only memory, if
Expand Down Expand Up @@ -160,7 +153,6 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)

} >ram :rom

/* ITIM SECTION
Expand All @@ -181,10 +173,28 @@ SECTIONS
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );

/* LIM SECTION
*
* The following sections contain data which is copied from read-only
* memory into a loosely integrated memory (LIM), which is shared with L2
* cache, during pre-main program initialization.
*
* Generally, the data copied into the LIM should be performance-critical
* functions which benefit from low instruction-fetch latency.
*/

.lim : ALIGN(8) {
*(.lim .lim.*)
} >ram AT>ram :lim_init

PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );

/* TEXT SECTION
*
* The following section contains the code of the program, excluding
* everything that's been allocated into the ITIM already
* everything that's been allocated into the ITIM/LIM already
*/

.text : {
Expand Down Expand Up @@ -261,7 +271,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
28 changes: 24 additions & 4 deletions bsp/qemu-sifive-e31/metal.default.lds
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Expand Up @@ -23,6 +23,7 @@ PHDRS
ram PT_LOAD;
itim_init PT_LOAD;
text PT_LOAD;
lim_init PT_LOAD;
}

SECTIONS
Expand Down Expand Up @@ -75,8 +76,10 @@ SECTIONS
PROVIDE(__metal_eccscrub_bit = 0);

/* The RAM memories map for ECC scrubbing */
/* Default zero-scrub to at most 64KB, for limiting RTL simulation run time. */
/* User is recommended to enable the full size for manual RTL simulation run! */
PROVIDE( metal_dtim_0_memory_start = 0x80000000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x400000 );
PROVIDE( metal_dtim_0_memory_end = 0x80000000 + 0x10000 );

/* ROM SECTION
*
Expand Down Expand Up @@ -156,7 +159,6 @@ SECTIONS
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)

} >rom :rom

/* ITIM SECTION
Expand All @@ -177,10 +179,28 @@ SECTIONS
PROVIDE( metal_segment_itim_target_start = ADDR(.itim) );
PROVIDE( metal_segment_itim_target_end = ADDR(.itim) + SIZEOF(.itim) );

/* LIM SECTION
*
* The following sections contain data which is copied from read-only
* memory into a loosely integrated memory (LIM), which is shared with L2
* cache, during pre-main program initialization.
*
* Generally, the data copied into the LIM should be performance-critical
* functions which benefit from low instruction-fetch latency.
*/

.lim : ALIGN(8) {
*(.lim .lim.*)
} >ram AT>rom :lim_init

PROVIDE( metal_segment_lim_source_start = LOADADDR(.lim) );
PROVIDE( metal_segment_lim_target_start = ADDR(.lim) );
PROVIDE( metal_segment_lim_target_end = ADDR(.lim) + SIZEOF(.lim) );

/* TEXT SECTION
*
* The following section contains the code of the program, excluding
* everything that's been allocated into the ITIM already
* everything that's been allocated into the ITIM/LIM already
*/

.text : {
Expand Down Expand Up @@ -257,7 +277,7 @@ SECTIONS
PROVIDE(metal_segment_stack_end = .);
} >ram :ram

.heap (NOLOAD) : ALIGN(4) {
.heap (NOLOAD) : ALIGN(8) {
PROVIDE( __end = . );
PROVIDE( __heap_start = . );
PROVIDE( metal_segment_heap_target_start = . );
Expand Down
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