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ARM: dts: qcom: Enable phy regulators for atoll
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Enable and add csiphy regulators in csiphy nodes for atoll.

Change-Id: Ic394ee0be86fb1b0cba8a51a8b134eb426681c78
Signed-off-by: Shravan Nevatia <[email protected]>
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@stefanhh0
Shravan Nevatia authored and stefanhh0 committed Aug 28, 2020
1 parent 75a49ef commit 33bd604
Showing 1 changed file with 32 additions and 12 deletions.
44 changes: 32 additions & 12 deletions arch/arm64/boot/dts/qcom/atoll-camera.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -25,11 +25,16 @@
reg-cam-base = <0x65000>;
interrupts = <0 477 0>;
interrupt-names = "csiphy";
regulator-names = "gdscr", "refgen";
regulator-names = "gdscr", "refgen",
"mipi-csi-vdd1", "mipi-csi-vdd2";
gdscr-supply = <&titan_top_gdsc>;
refgen-supply = <&refgen>;
csi-vdd-voltage = <900000>;
mipi-csi-vdd-supply = <&L4A>;
mipi-csi-vdd1-supply = <&L4A>;
mipi-csi-vdd2-supply = <&L3C>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 0 900000 1200000>;
rgltr-max-voltage = <0 0 900000 1200000>;
rgltr-load-current = <0 0 80000 80000>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
Expand Down Expand Up @@ -63,11 +68,16 @@
reg-cam-base = <0x66000>;
interrupts = <0 478 0>;
interrupt-names = "csiphy";
regulator-names = "gdscr", "refgen";
regulator-names = "gdscr", "refgen",
"mipi-csi-vdd1", "mipi-csi-vdd2";
gdscr-supply = <&titan_top_gdsc>;
refgen-supply = <&refgen>;
csi-vdd-voltage = <900000>;
mipi-csi-vdd-supply = <&L4A>;
mipi-csi-vdd1-supply = <&L4A>;
mipi-csi-vdd2-supply = <&L3C>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 0 900000 1200000>;
rgltr-max-voltage = <0 0 900000 1200000>;
rgltr-load-current = <0 0 80000 80000>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
Expand Down Expand Up @@ -101,11 +111,16 @@
reg-cam-base = <0x67000>;
interrupts = <0 479 0>;
interrupt-names = "csiphy";
regulator-names = "gdscr", "refgen";
regulator-names = "gdscr", "refgen",
"mipi-csi-vdd1", "mipi-csi-vdd2";
gdscr-supply = <&titan_top_gdsc>;
refgen-supply = <&refgen>;
csi-vdd-voltage = <900000>;
mipi-csi-vdd-supply = <&L4A>;
mipi-csi-vdd1-supply = <&L4A>;
mipi-csi-vdd2-supply = <&L3C>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 0 900000 1200000>;
rgltr-max-voltage = <0 0 900000 1200000>;
rgltr-load-current = <0 0 80000 80000>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
Expand Down Expand Up @@ -139,11 +154,16 @@
reg-cam-base = <0x68000>;
interrupts = <0 461 0>;
interrupt-names = "csiphy";
regulator-names = "gdscr", "refgen";
regulator-names = "gdscr", "refgen",
"mipi-csi-vdd1", "mipi-csi-vdd2";
gdscr-supply = <&titan_top_gdsc>;
refgen-supply = <&refgen>;
csi-vdd-voltage = <900000>;
mipi-csi-vdd-supply = <&L4A>;
mipi-csi-vdd1-supply = <&L4A>;
mipi-csi-vdd2-supply = <&L3C>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 0 900000 1200000>;
rgltr-max-voltage = <0 0 900000 1200000>;
rgltr-load-current = <0 0 80000 80000>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
Expand Down

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