Merge commit '40c77ca69b266c88ebbfdfdf806ed3033f40840e' into dev/msm-…

…4.14.c2-display

* commit '40c77ca69b266c88ebbfdfdf806ed3033f40840e':
  cpufreq: schedutil: Fix for limits update with fast switch enabled
  cpufreq: schedutil: Add fast switch to sugov_limits path
  soc: qcom: wda: Disable powersave work on deinitialization
  msm: kgsl: Change data type for GPU ib vote
  disp: msm: sde: add SSPP CP features to dirty list during IPC
  msm: ipa3: Fix to recycle buffers
  diag: Prevent using uninitialized mdlog session mask
  msm: kgsl: Ignore rgmu disable GDSC error
  power: smb5-lib: Report liquid presence status
  msm: kgsl: Add missing check for snapshot IB dump
  msm: kgsl: Snapshot all GMU memory blocks
  msm: kgsl: Snapshot GMU TCM registers separetely
  net: qrtr: mhi: Register for early notifications
  msm: kgsl: Fix drawqueue timer race condition
  msm: kgsl: Ensure GMU memory regions don't leak memory
  msm: kgsl: Update GMU snapshot section IDs
  ARM: dts: msm: Update GPU snapshot size
  msm: kgsl: Omit referencing pointers in traces
  arm64/iommu: handle atomic pool addresses in ->get_sgtable and ->mmap
  arm64/iommu: handle non-remapped addresses in ->mmap and ->get_sgtable
  ARM: dts: msm: register IPCR for early MHI notification
  mhi: cntrl: qcom: register for early error fatal notification
  mhi: core: add support for early error notifications
  diag: Update diag get log request structure
  msm: kgsl: Change throttling counter weight from 15% to 5%
  NFC: Fix device node probing issue
  mhi: core: add missing macro for MHI device vote
  msm: kgsl: show max gpu temperature
  soc: qcom: qmi_interface: Remove ineffective mutex lock from txn struct
  soc: qcom: qmi_interface: use qmi txn_lock to avoid use after free of txn
  sched/fair: Prevent tick path active migration to the same CPU
  msm: camera: isp: Halt device with the command parsed
  msm: vidc: add check to avoid out-of-buffer write
  usb: f_gsi: Don't enable IPA data path if connect channel fails
  mhi: core: expand MHI vote api to take optional parameter
  sched: fair: Add strict skip buddy support
  sched/fair: Allow load bigger task load balance when nr_running is 2
  msm: vidc: add additional check to avoid out of bound access
  USB: configfs: Send DISCONNECT uevent during UDC bind
  usb: dwc3-msm: Program MSB of doorbell register when using dummy_addr
  msm: ipa3: Drop WAN TX packets when pipe is down in ssr
  usb: dwc3-msm: Use dummy buffer as doorbell until GSI is ready
  ARM: msm: dts: modify rotator line width for sm8150
  Revert "drm/msm/sde: fix crtc enable check"
  ARM: dts: msm: add thermal zone names to sm8150
  msm: adsprpc: Fix integer overflow in refcount of map
  msm: kgsl: Ensure _free_pt() gets called on error case
  diag: dci: Correct out of bounds check in processing dci pkt rsp
  usb: dwc3: Flush bh work before disabling dwc3_irq
  power: step-chg-jeita: update jeita/step ranges to support signed threshold
  slim-msm-ngd: Create a IPC error logging file
  soc: qcom: dfc: Purge packets on flow delete
  Revert "diag: Clear memory device entries during mhi disconnect"
  ARM: dts: msm: Add GPU coresight properties for SM8150
  drm/msm/sde: fix crtc enable check
  usb: misc: nb7vpq904m: fix possible array overflow
  msm: ipa3: Handle missing cleanup in IMP_READY state on shutdown
  msm: npu: update performance mode during load network
  msm: npu: Allow user app to retrieve NPU version via get_property
  fbdev: msm: check the length of the external input buffer properly
  msm: kgsl: Ensure that thermal power level restrictions are enforced
  net: qrtr: Use skb with fragments in memory failure case
  media: uvcvideo: Fix 'type' check leading to overflow
  power: qpnp-qg: Add range checks to FIFO length
  msm: kgsl: Don't attempt the LLM/GLM handshake for a640 targets
  power: qpnp-smb5: Do not use ibatt based termination for QG PMICs
  msm: camera: sensor: Increase the eeprom map buffer count
  msm: vidc: refine clock calculation for both encoder and decoder
  msm: vidc: consider pipeline overhead factor for clock calculation
  msm: camera: reqmgr: Reset previous skipped slot if valid request
  drm/msm/sde: update mixercount check in writeback usecase
  msm: camera: crm: Increasing the device handles to 128
  f2fs: fix to avoid deadlock in f2fs_read_inline_dir()
  msm: kgsl: Correct snapshot over-write policy
  msm: camera: Adding device type to track device handles
  msm: camera: isp: Add support for initial frame drop
  esoc: Add mdm error-fatal notifier hook
  ARM: dts: msm: Increasing shared mem region size for SM6150 and sdmmagpie
  msm: camera: icp: Prevent out of bound access in acquire
  msm: camera: mem: Mutex before cpu_begin_access & cpu_end_access
  msm: camera: cpas: Check the HW state before accessing register
  msm: camera: cci: Add rd_done to handle read done operation
  msm: camera: crm: Increase the device handles to 128
  ARM: dts: msm: Increase camnoc bw margin for sdmmagpie
  msm: camera: fd: Remove duplicate "qcom,fd501" property
  msm: camera: reqmgr: Fix CRM shift one req issue
  msm: camera: icp: Mapping fw error numbers with error names
  msm: camera: isp: Prevent out of bounds read
  msm: camera: csiphy: correct DPHY bring up sequence
  msm: camera: Fix cpas axi clk rate overflow
  msm: kgsl: Correctly identify page faulting process
  msm: camera: reqmgr: Skip reset if no request from UMD

Change-Id: I7fb1713ebe3d786c7134db39033860114baa3df9
Signed-off-by: Abhijith Desai <[email protected]>

Documentation/devicetree/bindings/gpu/adreno.txt

@@ -207,6 +207,10 @@ Optional Properties:
 				Specify the name of GPU temperature sensor. This name will be used
 				to get the temperature from the thermal driver API.
 
+- tzone-names:
+				Specify the names of GPU thermal zones. These will be used
+				to get the temperature from the thermal driver API.
+
 - qcom,enable-midframe-timer:
 				Boolean. Enables the use of midframe sampling timer. This timer
 				samples the GPU powerstats if the cmdbatch expiry takes longer than

arch/arm64/boot/dts/qcom/sdmmagpie-camera.dtsi

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -409,18 +409,18 @@
 				};
 
 				iova-mem-region-shared {
-					/* Shared region is 100MB long */
+					/* Shared region is 150MB long */
 					iova-region-name = "shared";
 					iova-region-start = <0x7400000>;
-					iova-region-len = <0x6400000>;
+					iova-region-len = <0x9600000>;
 					iova-region-id = <0x1>;
 					status = "ok";
 				};
 
 				iova-mem-region-secondary-heap {
 					/* Secondary heap region is 1MB long */
 					iova-region-name = "secheap";
-					iova-region-start = <0xd800000>;
+					iova-region-start = <0x10A00000>;
 					iova-region-len = <0x100000>;
 					iova-region-id = <0x4>;
 					status = "ok";
@@ -429,16 +429,16 @@
 				iova-mem-region-io {
 					/* IO region is approximately 3 GB */
 					iova-region-name = "io";
-					iova-region-start = <0xda00000>;
-					iova-region-len = <0xace00000>;
+					iova-region-start = <0x10C00000>;
+					iova-region-len = <0xA9C00000>;
 					iova-region-id = <0x3>;
 					status = "ok";
 				};
 
 				iova-mem-qdss-region {
 					/* QDSS region is appropriate 1MB */
 					iova-region-name = "qdss";
-					iova-region-start = <0xd900000>;
+					iova-region-start = <0x10B00000>;
 					iova-region-len = <0x100000>;
 					iova-region-id = <0x5>;
 					qdss-phy-addr = <0x16790000>;
@@ -1076,7 +1076,7 @@
 		qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>;
 		control-camnoc-axi-clk;
 		camnoc-bus-width = <32>;
-		camnoc-axi-clk-bw-margin-perc = <10>;
+		camnoc-axi-clk-bw-margin-perc = <20>;
 		qcom,msm-bus,name = "cam_ahb";
 		qcom,msm-bus,num-cases = <6>;
 		qcom,msm-bus,num-paths = <1>;

arch/arm64/boot/dts/qcom/sm6150-camera.dtsi

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -318,10 +318,10 @@
 				};
 
 				iova-mem-region-shared {
-					/* Shared region is 100MB long */
+					/* Shared region is 150MB long */
 					iova-region-name = "shared";
 					iova-region-start = <0x7400000>;
-					iova-region-len = <0x6400000>;
+					iova-region-len = <0x9600000>;
 					iova-region-id = <0x1>;
 					iova-granularity = <0x15>;
 					status = "ok";
@@ -330,7 +330,7 @@
 				iova-mem-region-secondary-heap {
 					/* Secondary heap region is 1MB long */
 					iova-region-name = "secheap";
-					iova-region-start = <0xd800000>;
+					iova-region-start = <0x10A00000>;
 					iova-region-len = <0x100000>;
 					iova-region-id = <0x4>;
 					status = "ok";
@@ -339,16 +339,16 @@
 				iova-mem-region-io {
 					/* IO region is approximately 3 GB */
 					iova-region-name = "io";
-					iova-region-start = <0xd911000>;
-					iova-region-len = <0xd26ef000>;
+					iova-region-start = <0x10B11000>;
+					iova-region-len = <0xCF4EF000>;
 					iova-region-id = <0x3>;
 					status = "ok";
 				};
 
 				iova-mem-qdss-region {
 					/* qdss region is approximately 64K */
 					iova-region-name = "qdss";
-					iova-region-start = <0xd900000>;
+					iova-region-start = <0x10B00000>;
 					iova-region-len = <0x10000>;
 					iova-region-id = <0x5>;
 					qdss-phy-addr = <0x16790000>;

arch/arm64/boot/dts/qcom/sm8150-coresight.dtsi

@@ -635,25 +635,30 @@
 		ports {
 			#address-cells = <1>;
 			#size-cells = <0>;
-
 			port@0 {
 				reg = <0>;
 				funnel_in2_out_funnel_merg: endpoint {
 					remote-endpoint =
 					  <&funnel_merg_in_funnel_in2>;
 				};
 			};
-
 			port@1 {
 				reg = <2>;
 				funnel_in2_in_funnel_apss_merg: endpoint {
 					slave-mode;
 					remote-endpoint =
 					  <&funnel_apss_merg_out_funnel_in2>;
 				};
-
 			};
 			port@2 {
+				reg = <3>;
+				funnel_in2_in_funnel_gfx: endpoint {
+					slave-mode;
+					remote-endpoint =
+					  <&funnel_gfx_out_funnel_in2>;
+				};
+			};
+			port@3 {
 				reg = <4>;
 				funnel_in2_in_tpda_modem: endpoint {
 					slave-mode;
@@ -664,6 +669,48 @@
 		};
 	};
 
+	funnel_gfx: funnel@0x6943000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b908>;
+
+		reg = <0x6943000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-gfx";
+
+		clocks = <&clock_aop QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_gfx_out_funnel_in2: endpoint {
+					remote-endpoint =
+					  <&funnel_in2_in_funnel_gfx>;
+				};
+			};
+			port@1 {
+				reg = <1>;
+				funnel_gfx_in_gfx: endpoint {
+					slave-mode;
+					remote-endpoint =
+					  <&gfx_out_funnel_gfx>;
+				};
+			};
+			port@2 {
+				reg = <2>;
+				funnel_gfx_in_gfx_cx: endpoint {
+					slave-mode;
+					remote-endpoint =
+					  <&gfx_cx_out_funnel_gfx>;
+				};
+			};
+		};
+	};
+
 	tpda: tpda@6004000 {
 		compatible = "arm,primecell";
 		arm,primecell-periphid = <0x0003b969>;

arch/arm64/boot/dts/qcom/sm8150-gpu.dtsi

@@ -91,13 +91,15 @@
 
 		qcom,ubwc-mode = <3>;
 
-		qcom,snapshot-size = <1310720>; //bytes
+		qcom,snapshot-size = <0x200000>; //bytes
 
 		qcom,gpu-qdss-stm = <0x161c0000 0x40000>; // base addr, size
 
 		qcom,tsens-name = "tsens_tz_sensor12";
 		#cooling-cells = <2>;
 
+		tzone-names = "gpuss-0-usr", "gpuss-1-usr";
+
 		qcom,pm-qos-active-latency = <44>;
 
 		clocks = <&clock_gpucc GPU_CC_CXO_CLK>,
@@ -149,6 +151,36 @@
 		cache-slice-names = "gpu", "gpuhtw";
 		cache-slices = <&llcc 12>, <&llcc 11>;
 
+
+		qcom,gpu-coresights {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "qcom,gpu-coresight";
+
+			qcom,gpu-coresight@0 {
+				reg = <0>;
+				coresight-name = "coresight-gfx";
+				coresight-atid = <50>;
+				port {
+					gfx_out_funnel_gfx: endpoint {
+						remote-endpoint =
+						  <&funnel_gfx_in_gfx>;
+					};
+				};
+			};
+			qcom,gpu-coresight@1 {
+				reg = <1>;
+				coresight-name = "coresight-gfx-cx";
+				coresight-atid = <51>;
+				port {
+					gfx_cx_out_funnel_gfx: endpoint {
+						remote-endpoint =
+						  <&funnel_gfx_in_gfx_cx>;
+					};
+				};
+			};
+		};
+
 		qcom,l3-pwrlevels {
 			#address-cells = <1>;
 			#size-cells = <0>;

arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -425,6 +425,11 @@
 				mhi,interface-name = "rmnet_mhi";
 				mhi,mru = <0x4000>;
 			};
+
+			mhi_qrtr {
+				 mhi,chan = "IPCR";
+				 mhi,early-notify;
+			};
 		};
 	};
 };

arch/arm64/boot/dts/qcom/sm8150-sde.dtsi

@@ -1,4 +1,4 @@
-/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -394,7 +394,6 @@
 		qcom,mdss-default-ot-wr-limit = <32>;
 
 		qcom,mdss-sbuf-headroom = <20>;
-		qcom,mdss-rot-linewidth = <8192>;
 
 		cache-slice-names = "rotator";
 		cache-slices = <&llcc 4>;

arch/arm64/mm/dma-mapping.c

@@ -843,50 +843,56 @@ static int __iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
 {
 	struct vm_struct *area;
 	int ret;
+	unsigned long pfn = 0;
 
 	vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot,
 					     is_dma_coherent(dev, attrs));
 
 	if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
 		return ret;
 
-	if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) {
+	area = find_vm_area(cpu_addr);
+
+	if (area && area->pages)
+		return iommu_dma_mmap(area->pages, size, vma);
+	else if (!is_vmalloc_addr(cpu_addr))
+		pfn = page_to_pfn(virt_to_page(cpu_addr));
+	else if (is_vmalloc_addr(cpu_addr))
 		/*
-		 * DMA_ATTR_FORCE_CONTIGUOUS allocations are always remapped,
-		 * hence in the vmalloc space.
+		 * DMA_ATTR_FORCE_CONTIGUOUS and atomic pool allocations are
+		 * always remapped, hence in the vmalloc space.
 		 */
-		unsigned long pfn = vmalloc_to_pfn(cpu_addr);
-		return __swiotlb_mmap_pfn(vma, pfn, size);
-	}
+		pfn = vmalloc_to_pfn(cpu_addr);
 
-	area = find_vm_area(cpu_addr);
-	if (WARN_ON(!area || !area->pages))
-		return -ENXIO;
+	if (pfn)
+		return __swiotlb_mmap_pfn(vma, pfn, size);
 
-	return iommu_dma_mmap(area->pages, size, vma);
+	return -ENXIO;
 }
 
 static int __iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
 			       void *cpu_addr, dma_addr_t dma_addr,
 			       size_t size, unsigned long attrs)
 {
 	unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
+	struct page *page = NULL;
 	struct vm_struct *area = find_vm_area(cpu_addr);
 
-	if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) {
+	if (area && area->pages)
+		return sg_alloc_table_from_pages(sgt, area->pages, count, 0,
+					size, GFP_KERNEL);
+	else if (!is_vmalloc_addr(cpu_addr))
+		page = virt_to_page(cpu_addr);
+	else if (is_vmalloc_addr(cpu_addr))
 		/*
-		 * DMA_ATTR_FORCE_CONTIGUOUS allocations are always remapped,
-		 * hence in the vmalloc space.
+		 * DMA_ATTR_FORCE_CONTIGUOUS and atomic pool allocations
+		 * are always remapped, hence in the vmalloc space.
 		 */
-		struct page *page = vmalloc_to_page(cpu_addr);
-		return __swiotlb_get_sgtable_page(sgt, page, size);
-	}
+		page = vmalloc_to_page(cpu_addr);
 
-	if (WARN_ON(!area || !area->pages))
-		return -ENXIO;
-
-	return sg_alloc_table_from_pages(sgt, area->pages, count, 0, size,
-					 GFP_KERNEL);
+	if (page)
+		return __swiotlb_get_sgtable_page(sgt, page, size);
+	return -ENXIO;
 }
 
 static void __iommu_sync_single_for_cpu(struct device *dev,

drivers/bus/mhi/controllers/mhi_arch_qcom.c

@@ -189,6 +189,18 @@ static void mhi_arch_esoc_ops_power_off(void *priv, unsigned int flags)
 	pm_relax(&mhi_cntrl->mhi_dev->dev);
 }
 
+static void mhi_arch_esoc_ops_mdm_error(void *priv)
+{
+	struct mhi_controller *mhi_cntrl = priv;
+
+	MHI_LOG("Enter: mdm asserted\n");
+
+	/* transition MHI state into error state */
+	mhi_control_error(mhi_cntrl);
+
+	MHI_LOG("Exit\n");
+}
+
 static void mhi_bl_dl_cb(struct mhi_device *mhi_dev,
 			 struct mhi_result *mhi_result)
 {
@@ -362,6 +374,8 @@ int mhi_arch_pcie_init(struct mhi_controller *mhi_cntrl)
 				mhi_arch_esoc_ops_power_on;
 			esoc_ops->esoc_link_power_off =
 				mhi_arch_esoc_ops_power_off;
+			esoc_ops->esoc_link_mdm_crash =
+				mhi_arch_esoc_ops_mdm_error;
 
 			ret = esoc_register_client_hook(arch_info->esoc_client,
 							esoc_ops);