Merge #106

106: Set sys_ck frequency to pll1_p_ck when this is used r=richardeoin a=richardeoin Closes #105 Co-authored-by: Richard Meadows <[email protected]>
stm32-rs · Jul 24, 2020 · fc388fd · fc388fd
2 parents 297ce70 + 41f9469
commit fc388fd
Showing 1 changed file with 6 additions and 0 deletions.
diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs
@@ -566,6 +566,12 @@ impl Rcc {
         let (pll3_p_ck, pll3_q_ck, pll3_r_ck) =
             self.pll3_setup(rcc, &self.config.pll3);
 
+        let sys_ck = if sys_use_pll1_p {
+            pll1_p_ck.unwrap() // Must have been set by sys_ck_setup
+        } else {
+            sys_ck
+        };
+
         // hsi_ck = HSI. This routine does not support HSIDIV != 1. To
         // do so it would need to ensure all PLLxON bits are clear
         // before changing the value of HSIDIV