system(H5): update STM32H5xx CMSIS Drivers to v1.3.1

Included in STM32CubeH5 FW v1.4.0

Signed-off-by: Frederic Pillon <[email protected]>

system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h

@@ -186,7 +186,7 @@ typedef enum
 /** @} */ /* End of group Configuration_of_CMSIS */
 
 
-#include <core_cm33.h>                       /*!< ARM Cortex-M33 processor and core peripherals */
+#include "core_cm33.h"                       /*!< ARM Cortex-M33 processor and core peripherals */
 #include "system_stm32h5xx.h"                /*!< STM32H5xx System */
 
 
@@ -13300,7 +13300,7 @@ typedef struct
 /******************************** SPI Instances *******************************/
 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI3_NS))
 
-#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == NULL)
+#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) ==  ((SPI_TypeDef *) 0xDEADDEADUL))
 
 #define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI3_NS))
 

system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h523xx.h

@@ -215,7 +215,7 @@ typedef enum
 /** @} */ /* End of group Configuration_of_CMSIS */
 
 
-#include <core_cm33.h>                       /*!< ARM Cortex-M33 processor and core peripherals */
+#include "core_cm33.h"                       /*!< ARM Cortex-M33 processor and core peripherals */
 #include "system_stm32h5xx.h"                /*!< STM32H5xx System */
 
 

system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h

@@ -218,7 +218,7 @@ typedef enum
 /** @} */ /* End of group Configuration_of_CMSIS */
 
 
-#include <core_cm33.h>                       /*!< ARM Cortex-M33 processor and core peripherals */
+#include "core_cm33.h"                       /*!< ARM Cortex-M33 processor and core peripherals */
 #include "system_stm32h5xx.h"                /*!< STM32H5xx System */
 
 

system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h

@@ -234,7 +234,7 @@ typedef enum
 /** @} */ /* End of group Configuration_of_CMSIS */
 
 
-#include <core_cm33.h>                       /*!< ARM Cortex-M33 processor and core peripherals */
+#include "core_cm33.h"                       /*!< ARM Cortex-M33 processor and core peripherals */
 #include "system_stm32h5xx.h"                /*!< STM32H5xx System */
 
 

system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h

@@ -239,7 +239,7 @@ typedef enum
 /** @} */ /* End of group Configuration_of_CMSIS */
 
 
-#include <core_cm33.h>                       /*!< ARM Cortex-M33 processor and core peripherals */
+#include "core_cm33.h"                       /*!< ARM Cortex-M33 processor and core peripherals */
 #include "system_stm32h5xx.h"                /*!< STM32H5xx System */
 
 

system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h

@@ -242,7 +242,7 @@ typedef enum
 /** @} */ /* End of group Configuration_of_CMSIS */
 
 
-#include <core_cm33.h>                       /*!< ARM Cortex-M33 processor and core peripherals */
+#include "core_cm33.h"                       /*!< ARM Cortex-M33 processor and core peripherals */
 #include "system_stm32h5xx.h"                /*!< STM32H5xx System */
 
 

system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h

@@ -57,7 +57,7 @@
    application
   */
 
-#if !defined (STM32H573xx) && !defined (STM32H563xx)    \
+#if !defined (STM32H573xx) && !defined (STM32H563xx) \
     && !defined (STM32H562xx) && !defined (STM32H503xx) \
     && !defined (STM32H533xx) && !defined (STM32H523xx)
   /* #define STM32H573xx  */   /*!< STM32H573xx Devices   */
@@ -81,12 +81,12 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number 1.3.0
+  * @brief CMSIS Device version number 1.3.1
   */
-#define __STM32H5_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32H5_CMSIS_VERSION_SUB1   (0x03U) /*!< [23:16] sub1 version */
-#define __STM32H5_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
-#define __STM32H5_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32H5_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32H5_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+#define __STM32H5_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32H5_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
 #define __STM32H5_CMSIS_VERSION        ((__STM32H5_CMSIS_VERSION_MAIN << 24U)\
                                        |(__STM32H5_CMSIS_VERSION_SUB1 << 16U)\
                                        |(__STM32H5_CMSIS_VERSION_SUB2 << 8U )\

system/Drivers/CMSIS/Device/ST/STM32H5xx/Release_Notes.html

@@ -30,11 +30,22 @@ <h1 id="release-notes-for-stm32h5xx-cmsis">Release Notes for <mark> STM32H5xx C
 <div class="col-sm-12 col-lg-8">
 <h1 id="update-history"><strong>Update History</strong></h1>
 <div class="collapse">
-<input type="checkbox" id="collapse-section4" Checked aria-hidden="true"> <label for="collapse-section4" checked aria-hidden="true"><strong>V1.3.0 / 05-June-2024</strong></label>
+<input type="checkbox" id="collapse-section5" Checked aria-hidden="true"> <label for="collapse-section5" checked aria-hidden="true"><strong>V1.3.1 / 30-October-2024</strong></label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
 <p>CMSIS Device Maintenance Release version of bits and registers definition aligned with <strong>RM0481</strong> (STM32H5 reference manual)</p>
 <ul>
+<li>Update to use #include "core_cm33.h" instead of #include &lt;core_cm33.h&gt; to force the first searches for the core_cm33.h file in the same directory as the file that contains the #include directive (Drivers\CMSIS\Core\Include)</li>
+<li>Update IS_SPI_LIMITED macro to return an essential boolean</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" checked aria-hidden="true"><strong>V1.3.0 / 05-June-2024</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<p>CMSIS Device Maintenance Release version of bits and registers definition aligned with <strong>RM0481</strong> (STM32H5 reference manual)</p>
+<ul>
 <li>Add RNG_CR_NIST_VALUE, RNG_NSCR_NIST_VALUE and RNG_HTCR_NIST_VALUE defines</li>
 <li>Add Bits definition for RNG_NSCR register : Add RNG_NSCR_EN_OSC1, RNG_NSCR_EN_OSC2, RNG_NSCR_EN_OSC3, RNG_NSCR_EN_OSC4, RNG_NSCR_EN_OSC5 and RNG_NSCR_EN_OSC6 defines</li>
 <li>Add USART_DMAREQUESTS_SW_WA define</li>
@@ -50,7 +61,7 @@ <h2 id="main-changes">Main Changes</h2>
 <div class="collapse">
 <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" checked aria-hidden="true"><strong>V1.2.0 / 09-February-2024</strong></label>
 <div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
 <ul>
 <li>First official release of STM32H5xx CMSIS drivers to support <strong>STM32H533xx and STM32H523xx</strong> devices</li>
 <li>Add bit definition for I3C_BCR register</li>
@@ -69,7 +80,7 @@ <h2 id="main-changes-1">Main Changes</h2>
 <div class="collapse">
 <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" checked aria-hidden="true"><strong>V1.1.0 / 07-June-2023</strong></label>
 <div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
 <ul>
 <li>Add DUA addresses constants definitions for STM32H573xx devices only</li>
 <li>Fix wrong definition of IS_TIM_CLOCKSOURCE_TIX_INSTANCE &amp; IS_TIM_TISEL_INSTANCE macros</li>
@@ -80,7 +91,7 @@ <h2 id="main-changes-2">Main Changes</h2>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" checked aria-hidden="true"><strong>V1.0.0 / 10-February-2023</strong></label>
 <div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
 <ul>
 <li>First official release version of bits and registers definition aligned with RM0481 and RM0492 (STM32H5 reference manuals)</li>
 </ul>

system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md

@@ -9,7 +9,7 @@
   * STM32F7: 1.2.9
   * STM32G0: 1.4.4
   * STM32G4: 1.2.5
-  * STM32H5: 1.3.0
+  * STM32H5: 1.3.1
   * STM32H7: 1.10.4
   * STM32L0: 1.9.3
   * STM32L1: 2.3.3