Merge pull request #2556 from thernstig/C071RBTx

feat: Generic variant C071RBTx support
stm32duino · Nov 13, 2024 · 7a2786a · 7a2786a
2 parents dffdc7a + a8a6903
commit 7a2786a
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Showing 8 changed files with 343 additions and 4 deletions.
diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json
@@ -49,6 +49,7 @@
             "GENERIC_C031C4UX",
             "GENERIC_C031C6TX",
             "GENERIC_C031F4PX",
+            "GENERIC_C071R8TX",
             "GENERIC_F031C4TX",
             "GENERIC_F031E6YX",
             "GENERIC_F031F4PX",

diff --git a/CI/build/conf/cores_config_ci.json b/CI/build/conf/cores_config_ci.json
@@ -49,6 +49,7 @@
             "GENERIC_C031C4UX",
             "GENERIC_C031C6TX",
             "GENERIC_C031F4PX",
+            "GENERIC_C071R8TX",
             "GENERIC_F031C4TX",
             "GENERIC_F031E6YX",
             "GENERIC_F031F4PX",

diff --git a/README.md b/README.md
@@ -214,6 +214,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
 | :green_heart: | STM32C011J4<br>STM32C011J6 | Generic Board | *2.8.0* |  |
 | :green_heart: | STM32C031C4<br>STM32C031C6 | Generic Board | *2.5.0* |  |
 | :green_heart: | STM32C031F4<br>STM32C031F6 | Generic Board | *2.6.0* |  |
+| :yellow_heart: | STM32C071R8<br>STM32C071RB | Generic Board | **2.9.0** | |
 
 ### Generic STM32F0 boards
 

diff --git a/boards.txt b/boards.txt
@@ -1668,6 +1668,22 @@ GenC0.menu.pnum.GENERIC_C031F6PX.build.product_line=STM32C031xx
 GenC0.menu.pnum.GENERIC_C031F6PX.build.variant=STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P
 GenC0.menu.pnum.GENERIC_C031F6PX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C031.svd
 
+# Generic C071R8Tx
+GenC0.menu.pnum.GENERIC_C071R8TX=Generic C071R8Tx
+GenC0.menu.pnum.GENERIC_C071R8TX.upload.maximum_size=65536
+GenC0.menu.pnum.GENERIC_C071R8TX.upload.maximum_data_size=24576
+GenC0.menu.pnum.GENERIC_C071R8TX.build.board=GENERIC_C071R8TX
+GenC0.menu.pnum.GENERIC_C071R8TX.build.product_line=STM32C071xx
+GenC0.menu.pnum.GENERIC_C071R8TX.build.variant=STM32C0xx/C071R(8-B)T
+
+# Generic C071RBTx
+GenC0.menu.pnum.GENERIC_C071RBTX=Generic C071RBTx
+GenC0.menu.pnum.GENERIC_C071RBTX.upload.maximum_size=131072
+GenC0.menu.pnum.GENERIC_C071RBTX.upload.maximum_data_size=24576
+GenC0.menu.pnum.GENERIC_C071RBTX.build.board=GENERIC_C071RBTX
+GenC0.menu.pnum.GENERIC_C071RBTX.build.product_line=STM32C071xx
+GenC0.menu.pnum.GENERIC_C071RBTX.build.variant=STM32C0xx/C071R(8-B)T
+
 # Upload menu
 GenC0.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD)
 GenC0.menu.upload_method.swdMethod.upload.protocol=swd

diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake
@@ -7130,6 +7130,114 @@ target_compile_options(GENERIC_C031F6PX_serial_none INTERFACE
   "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
 )
 
+# GENERIC_C071R8TX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_C071R8TX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C071R(8-B)T")
+set(GENERIC_C071R8TX_MAXSIZE 65536)
+set(GENERIC_C071R8TX_MAXDATASIZE 24576)
+set(GENERIC_C071R8TX_MCU cortex-m0plus)
+set(GENERIC_C071R8TX_FPCONF "-")
+add_library(GENERIC_C071R8TX INTERFACE)
+target_compile_options(GENERIC_C071R8TX INTERFACE
+  "SHELL:-DSTM32C071xx  -D__CORTEX_SC=0"
+  "SHELL:"
+  "SHELL:"
+  "SHELL: "
+  -mcpu=${GENERIC_C071R8TX_MCU}
+)
+target_compile_definitions(GENERIC_C071R8TX INTERFACE
+  "STM32C0xx"
+	"ARDUINO_GENERIC_C071R8TX"
+	"BOARD_NAME=\"GENERIC_C071R8TX\""
+	"BOARD_ID=GENERIC_C071R8TX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_C071R8TX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/
+  ${GENERIC_C071R8TX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_C071R8TX INTERFACE
+  "LINKER:--default-script=${GENERIC_C071R8TX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=65536"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=24576"
+  "SHELL: "
+  -mcpu=${GENERIC_C071R8TX_MCU}
+)
+
+add_library(GENERIC_C071R8TX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_C071R8TX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_C071R8TX_serial_generic INTERFACE)
+target_compile_options(GENERIC_C071R8TX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_C071R8TX_serial_none INTERFACE)
+target_compile_options(GENERIC_C071R8TX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+
+# GENERIC_C071RBTX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_C071RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C071R(8-B)T")
+set(GENERIC_C071RBTX_MAXSIZE 131072)
+set(GENERIC_C071RBTX_MAXDATASIZE 24576)
+set(GENERIC_C071RBTX_MCU cortex-m0plus)
+set(GENERIC_C071RBTX_FPCONF "-")
+add_library(GENERIC_C071RBTX INTERFACE)
+target_compile_options(GENERIC_C071RBTX INTERFACE
+  "SHELL:-DSTM32C071xx  -D__CORTEX_SC=0"
+  "SHELL:"
+  "SHELL:"
+  "SHELL: "
+  -mcpu=${GENERIC_C071RBTX_MCU}
+)
+target_compile_definitions(GENERIC_C071RBTX INTERFACE
+  "STM32C0xx"
+	"ARDUINO_GENERIC_C071RBTX"
+	"BOARD_NAME=\"GENERIC_C071RBTX\""
+	"BOARD_ID=GENERIC_C071RBTX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_C071RBTX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/
+  ${GENERIC_C071RBTX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_C071RBTX INTERFACE
+  "LINKER:--default-script=${GENERIC_C071RBTX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=131072"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=24576"
+  "SHELL: "
+  -mcpu=${GENERIC_C071RBTX_MCU}
+)
+
+add_library(GENERIC_C071RBTX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_C071RBTX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_C071RBTX_serial_generic INTERFACE)
+target_compile_options(GENERIC_C071RBTX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_C071RBTX_serial_none INTERFACE)
+target_compile_options(GENERIC_C071RBTX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+
 # GENERIC_F030C6TX
 # -----------------------------------------------------------------------------
 

diff --git a/libraries/Wire/src/utility/twi.c b/libraries/Wire/src/utility/twi.c
@@ -763,8 +763,8 @@ void i2c_init(i2c_t *obj, uint32_t timing, uint32_t ownAddress)
           __HAL_RCC_I2C2_FORCE_RESET();
           __HAL_RCC_I2C2_RELEASE_RESET();
           obj->irq = I2C2_EV_IRQn;
-#if !defined(STM32F0xx) && !defined(STM32G0xx) && !defined(STM32L0xx) && \
-    !defined(STM32U0xx)
+#if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && \
+    !defined(STM32L0xx) && !defined(STM32U0xx)
           obj->irqER = I2C2_ER_IRQn;
 #endif /* !STM32F0xx && !STM32G0xx && !STM32L0xx && !STM32U0xx */
           i2c_handles[I2C2_INDEX] = handle;

diff --git a/variants/STM32C0xx/C071R(8-B)T/generic_clock.c b/variants/STM32C0xx/C071R(8-B)T/generic_clock.c
@@ -12,6 +12,7 @@
  */
 #if defined(ARDUINO_GENERIC_C071R8TX) || defined(ARDUINO_GENERIC_C071RBTX)
 #include "pins_arduino.h"
+#include "stm32yyxx_ll_utils.h"
 
 /**
   * @brief  System Clock Configuration
@@ -20,8 +21,32 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
+
+  /* HSI configuration and activation */
+  LL_RCC_HSI_Enable();
+  while (LL_RCC_HSI_IsReady() != 1) {
+  }
+
+  LL_RCC_HSI_SetCalibTrimming(64);
+  LL_RCC_SetHSIDiv(LL_RCC_HSI_DIV_1);
+  /* Set AHB prescaler*/
+  LL_RCC_SetAHBPrescaler(LL_RCC_HCLK_DIV_1);
+
+  /* Sysclk activation on the HSI */
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+  while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
+  }
+
+  /* Set APB1 prescaler*/
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+  /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
+  LL_SetSystemCoreClock(48000000);
+
+  /* Update the time base */
+  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */