Verilog Utility Modules

Collection of some utility modules written in Verilog.

Included Modules

Module	File
Pseudo-Random Number Generator	pseudoRandNumGen.v
Linear Shift Registers	pseudoRandNumGen.v
Seven Segment Display controller	ssd_util.v
Seven Segment Display encoder	ssd_util.v
Button debouncer	btn_debouncer.v
Clock dividers	clk_div.v
Counters	counters.v
Timer	timer.v
Edge detect	edge_detect.v
GP Pulse-Width modulators	pwm.v
RGB LED Pulse-Width modulator	rgn_led_pwm.v
Adders	adders.v
Keypad Decoder	keypad.v
Parameterized Clock Generator	clkGenParam.v
8x8 LED Matrix controller	led_matrix.v
Button Switch Converters	btn_sw.v
Hexadecimal to decimal converter	hextoDec.v
Modulo Calculator	modulo.v
Fundamental Logic Gates	basic_gates.v
Parallel to Serial Converter	parallel_to_serial.v
FIFO with Flexible Size	fifo_flex.v
FIFO with Circular Buffer	fifo.v
Tri-State Buffer	tribuff.v

Primitive	File
Bi-Directional Buffer	IOBUF.v

CERN Open Hardware Licence Version 2 - Weakly Reciprocal

Name		Name	Last commit message	Last commit date
Latest commit History 63 Commits
Modules		Modules
Xilinx_Primitives		Xilinx_Primitives
.gitignore		.gitignore
LICENCE		LICENCE
README.md		README.md
fifo_tb.v		fifo_tb.v