MinRoot VDF Hardware Engine

System Verilog implementation of the MinRoot VDF using the Pasta Curves. The intended usage is within an ASIC to be developed for the Ethereum 2 and Filecoin protocols.

Contents

doc - Command and status register (CSR) details in html format

rtl

• ahb - AHB subordinate CSR bridge
• components - primitive components (synchronizer, clock gate, compression tree)
• csr - primitives and specific CSRs for MinRoot, utilized reggen from the OpenTitan project
• minroot_engine - main engine performing MinRoot over pasta curves
• top - top level

tb - Basic testbench to demonstrate functionality

Test

The environment is currently setup for VCS. No other simulators have been attempted.

To run the test:

cd tb
make

License

This repository is licensed under the Apache License Version 2.0 software license.