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Add test and fix for long log line #219
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Original file line number | Diff line number | Diff line change |
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import cocotb | ||
from cocotb.triggers import Timer | ||
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import pytest | ||
from cocotb_test.simulator import run | ||
import os | ||
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hdl_dir = os.path.dirname(__file__) | ||
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@cocotb.test() | ||
def run_test_long_log(dut): | ||
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yield Timer(1) | ||
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dut._log.info("BEFORE") | ||
dut._log.info("LONGLOG" * 100000) | ||
dut._log.info("AFTER") | ||
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@pytest.mark.skipif(os.getenv("SIM") == "ghdl", reason="VHDL not suported") | ||
def test_long_log(): | ||
run(verilog_sources=[os.path.join(hdl_dir, "dff.sv")], module="test_long_log", toplevel="dff_test") |