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synopsys

Here are 36 public repositories matching this topic...

limerainne / Dockerize-EDA

[WIP] Dockerize Synopsys/Cadence EDA tools

dockerfile eda synopsys cadence

Updated Mar 29, 2019
Dockerfile

bojackchen / digital-flow

This is a tutorial on standard digital design flow

synthesis synopsys logic-synthesis verilog-hdl timing-analysis

Updated May 24, 2021
Tcl

foss-for-synopsys-dwc-arc-processors / embarc_osp

embARC Open Software Platform (OSP) - An embedded software distribution for IoT and other embedded applications for ARC

iot internet-of-things iot-platform arc synopsys iot-framework processors

Updated Apr 25, 2024
C

kaushalmodi / custom_uvm_report_server

Customized UVM Report Server

vcs systemverilog synopsys uvm cadence xcelium

Updated Feb 10, 2020
SystemVerilog

mperov / fixSegfaultVCS

There is segmentation fault of VCS which should be fixed.

Updated Sep 19, 2023
Python

iDoka / mastering-fpgasic-book

📖 Mastering FPGASIC Book

engineering asic fpga hardware book vhdl intel verilog xilinx diy altera synopsys hdl vlsi cadence gateware fpgasic

Updated Nov 28, 2021

minhoolee / Synopsys-Project-2017

A deep learning based bioinformatics project on epigenetics in Type 2 Diabetes.

bioinformatics deep-learning genetics keras diabetes synopsys

Updated Mar 25, 2023
Jupyter Notebook

Juanx65 / RISC-V

Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.

visual-studio-code synopsys risc-v mobaxterm

Updated Sep 8, 2024
Verilog

gabrielganzer / RTL-PowerOptimization

Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.

script optimization polito tcl project synopsys dvs primetime voltage-scaling design-vision synopsys-dc

Updated Jun 9, 2021
Verilog

lnishan / Curriculum-Vitae

🌟 Jasmine "lnishan" Chen's Curriculum Vitae (CV) in Markdown

computer-science education google internship skills curriculum-vitae taiwan competitive-programming programming-contests taipei synopsys

Updated May 23, 2018
CSS

erihsu / tf-parser

Technology file parser in Rust

parser nom synopsys integrated-circuits electronic-design-automation

Updated Apr 6, 2021
Rust

kkiningh / synthesis-example

Example of a full DC synthesis script for a simple design

verilog synthesis synopsys vlsi designcompiler

Updated Feb 25, 2019
Tcl

gabrielganzer / DLX-Microprocessor

Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.

optimization polito microprocessor synthesis synopsys dlx cadence digital-design physical-design dlx-microprocessor

Updated Jun 9, 2021
Verilog

rabieifk / Synthesis-and-TCL-Scripting

Exploring Synopsys(R) synthesis tools

mips cad synopsys

Updated Jan 10, 2021
Verilog

jenkinsci / synopsys-security-scan-plugin

Synopsys Security Plugin provides functionality for performing Security Scan with Black Duck, Coverity and Polaris.

java jenkins-plugin spring-integration synopsys blackduck coverity polaris security-scan

Updated Nov 25, 2024
Java

parthpower / DCC_Basic

Typical project for Synopsys DC Compiler

tcl synopsys primetime dc-compiler

Updated Jun 21, 2018
Tcl

Vincenzo-Petrolo / DLX-RISC-microprocessor

DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino

vhdl verilog microprocessor synopsys dlx dlx-instruction-set dlx-processor innovus

Updated Jan 16, 2023
Verilog

iDoka / iDoka.github.io

iDoka's web page on Github

cryptography embedded asic fpga hardware dsp hacking rtl xilinx sdr sha256 can-bus gnss synopsys soc vlsi hw cadence automotive-electronics

Updated Sep 19, 2019

thaljef / synopsys-detect-bash-completion

Command completion for Synopsys (Black Duck) Detect commands

bash-completion synopsys security-tools blackduck

Updated Dec 16, 2021
Shell

kkiningh / asic-design

A small collection of tutorials and tools for ASIC design.

asic verilog systemverilog synopsys

Updated May 16, 2017
SystemVerilog

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