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Generate UVM register model from compiled SystemRDL input

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build PyPI - Python Version

PeakRDL-uvm

Generate UVM register model from compiled SystemRDL input.

For the command line tool, see the PeakRDL project.

Installing

Install from PyPi using pip:

python3 -m pip install peakrdl-uvm

Example

The easiest way to use PeakRDL-uvm is via the PeakRDL command line tool:

# Install the command line tool
python3 -m pip install peakrdl

# Generate UVM
peakrdl uvm your_design.rdl -o your_design.sv

Reference

UVMExporter(**kwargs)

Constructor for the UVM Exporter class

Optional Parameters

  • user_template_dir
    • Path to a directory where user-defined template overrides are stored.
  • user_template_context
    • Additional context variables to load into the template namespace.

UVMExporter.export(node, path, **kwargs)

Perform the export!

Parameters

  • node
    • Top-level node to export. Can be the top-level RootNode or any internal AddrmapNode.
  • path
    • Output file.

Optional Parameters

  • export_as_package
    • If True (Default), UVM register model is exported as a SystemVerilog package. Package name is based on the output file name.
    • If False, register model is exported as an includable header.
  • reuse_class_definitions
    • If True (Default), exporter attempts to re-use class definitions where possible. Class names are based on the lexical scope of the original SystemRDL definitions.
    • If False, class definitions are not reused. Class names are based on the instance's hierarchical path.
  • use_uvm_factory
    • If True, class definitions and class instances are created using the UVM factory.
    • If False (Default), UVM factory is disabled. Classes are created directly via new() constructors.

API Example

Pass the elaborated output of the SystemRDL Compiler to the exporter.

import sys
from systemrdl import RDLCompiler, RDLCompileError
from peakrdl_uvm import UVMExporter

rdlc = RDLCompiler()

try:
    rdlc.compile_file("path/to/my.rdl")
    root = rdlc.elaborate()
except RDLCompileError:
    sys.exit(1)

exporter = UVMExporter()
exporter.export(root, "test.sv")

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Generate UVM register model from compiled SystemRDL input

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  • Python 51.2%
  • SystemVerilog 45.8%
  • Shell 3.0%