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fix msvc warnings
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marcomoerz committed Aug 23, 2024
1 parent 3adf09e commit 22a95ed
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Showing 11 changed files with 62 additions and 62 deletions.
4 changes: 2 additions & 2 deletions src/DRAMPower/DRAMPower/memspec/MemSpecDDR4.h
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Expand Up @@ -77,8 +77,8 @@ class MemSpecDDR4 final : public MemSpec<DRAMUtils::MemSpec::MemSpecDDR4>

uint64_t timeToCompletion(CmdType type) override;

unsigned numberOfBankGroups;
unsigned numberOfRanks;
uint64_t numberOfBankGroups;
uint64_t numberOfRanks;

double vddq;

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12 changes: 6 additions & 6 deletions src/DRAMPower/DRAMPower/memspec/MemSpecDDR5.h
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Expand Up @@ -38,9 +38,9 @@ namespace DRAMPower {
uint64_t timeToCompletion(CmdType type) override;


unsigned numberOfBankGroups;
unsigned banksPerGroup;
unsigned numberOfRanks;
uint64_t numberOfBankGroups;
uint64_t banksPerGroup;
uint64_t numberOfRanks;

double vddq;

Expand Down Expand Up @@ -94,9 +94,9 @@ namespace DRAMPower {
};

struct DataRateSpec {
uint32_t commandBusRate;
uint32_t dataBusRate;
uint32_t dqsBusRate;
uint64_t commandBusRate;
uint64_t dataBusRate;
uint64_t dqsBusRate;
};

struct BankWiseParams
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8 changes: 4 additions & 4 deletions src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR4.h
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Expand Up @@ -37,9 +37,9 @@ class MemSpecLPDDR4 final : public MemSpec<DRAMUtils::MemSpec::MemSpecLPDDR4>
~MemSpecLPDDR4() = default;
uint64_t timeToCompletion(CmdType type) override;

unsigned numberOfBankGroups;
unsigned banksPerGroup;
unsigned numberOfRanks;
uint64_t numberOfBankGroups;
uint64_t banksPerGroup;
uint64_t numberOfRanks;

double vddq;

Expand Down Expand Up @@ -110,7 +110,7 @@ class MemSpecLPDDR4 final : public MemSpec<DRAMUtils::MemSpec::MemSpecLPDDR4>
// ACT Standby power factor
double bwPowerFactRho;
// Self-Refresh power factor
uint64_t bwPowerFactSigma;
double bwPowerFactSigma;
// Whether PASR is enabled ( true : enabled )
bool flgPASR;
// PASR mode utilized (int 0-7)
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6 changes: 3 additions & 3 deletions src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR5.h
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Expand Up @@ -42,9 +42,9 @@ namespace DRAMPower {
uint64_t timeToCompletion(CmdType type) override;


unsigned numberOfBankGroups;
unsigned banksPerGroup;
unsigned numberOfRanks;
uint64_t numberOfBankGroups;
uint64_t banksPerGroup;
uint64_t numberOfRanks;
std::size_t perTwoBankOffset = 8;
BankArchitectureMode bank_arch;
bool wckAlwaysOnMode;
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6 changes: 3 additions & 3 deletions src/DRAMPower/DRAMPower/standards/lpddr5/LPDDR5.cpp
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Expand Up @@ -586,9 +586,9 @@ namespace DRAMPower {
stats.readBus = readBus.get_stats(timestamp);
stats.writeBus = writeBus.get_stats(timestamp);

stats.clockStats = 2.0 * clock.get_stats_at(timestamp);
stats.wClockStats = 2.0 * wck.get_stats_at(timestamp);
stats.readDQSStats = 2.0 * readDQS.get_stats_at(timestamp);
stats.clockStats = 2 * clock.get_stats_at(timestamp);
stats.wClockStats = 2 * wck.get_stats_at(timestamp);
stats.readDQSStats = 2 * readDQS.get_stats_at(timestamp);

return stats;
}
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2 changes: 1 addition & 1 deletion src/DRAMPower/DRAMPower/util/dynamic_bitset.cpp
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Expand Up @@ -10,7 +10,7 @@ dynamic_bitset::dynamic_bitset()
dynamic_bitset::dynamic_bitset(std::size_t num_bits)
: buffer(num_bits, 0) {};

dynamic_bitset::dynamic_bitset(std::size_t num_bits, unsigned long value)
dynamic_bitset::dynamic_bitset(std::size_t num_bits, uint64_t value)
: buffer(num_bits)
{
std::size_t accumulator = 1;
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2 changes: 1 addition & 1 deletion src/DRAMPower/DRAMPower/util/dynamic_bitset.h
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Expand Up @@ -22,7 +22,7 @@ class dynamic_bitset
public:
explicit dynamic_bitset();
explicit dynamic_bitset(std::size_t num_bits);
explicit dynamic_bitset(std::size_t num_bits, unsigned long value = 0);
explicit dynamic_bitset(std::size_t num_bits, uint64_t value = 0);
public:
dynamic_bitset(const dynamic_bitset&) = default;
dynamic_bitset(dynamic_bitset&&) noexcept = default;
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50 changes: 25 additions & 25 deletions tests/tests_drampower/interface/test_interface_ddr4.cpp
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Expand Up @@ -132,14 +132,14 @@ TEST_F(DDR4_WindowStats_Tests, Pattern_0) {
// ("size in bits" / bus_size) / bus_rate
// read and write have the same length
// number of cycles per write/read
int number_of_cycles = (SZ_BITS(wr_data) / 8) / spec->dataRate;
uint64_t number_of_cycles = (SZ_BITS(wr_data) / 8) / spec->dataRate;

// In this example read data and write data are the same size, so stats should be the same
// DQs modelled as single line
int DQS_ones = number_of_cycles * spec->dataRate;
int DQS_zeros = DQS_ones;
int DQS_zeros_to_ones = DQS_ones;
int DQS_ones_to_zeros = DQS_zeros;
uint64_t DQS_ones = number_of_cycles * spec->dataRate;
uint64_t DQS_zeros = DQS_ones;
uint64_t DQS_zeros_to_ones = DQS_ones;
uint64_t DQS_ones_to_zeros = DQS_zeros;
EXPECT_EQ(stats.writeDQSStats.ones, DQS_ones);
EXPECT_EQ(stats.writeDQSStats.zeroes, DQS_zeros);
EXPECT_EQ(stats.writeDQSStats.ones_to_zeroes, DQS_zeros_to_ones);
Expand Down Expand Up @@ -194,12 +194,12 @@ TEST_F(DDR4_WindowStats_Tests, Pattern_1) {
// DQs bus
// For write and read the number of clock cycles the strobes stay on is
// (("number of writes/reads" * "size in bits") / bus_size) / bus_rate
int number_of_cycles = ((2 * SZ_BITS(wr_data)) / 8) / spec->dataRate;
uint64_t number_of_cycles = ((2 * SZ_BITS(wr_data)) / 8) / spec->dataRate;

int DQS_ones = number_of_cycles * spec->dataRate;
int DQS_zeros = DQS_ones;
int DQS_zeros_to_ones = DQS_ones;
int DQS_ones_to_zeros = DQS_zeros;
uint64_t DQS_ones = number_of_cycles * spec->dataRate;
uint64_t DQS_zeros = DQS_ones;
uint64_t DQS_zeros_to_ones = DQS_ones;
uint64_t DQS_ones_to_zeros = DQS_zeros;
EXPECT_EQ(stats.writeDQSStats.ones, DQS_ones);
EXPECT_EQ(stats.writeDQSStats.zeroes, DQS_zeros);
EXPECT_EQ(stats.writeDQSStats.ones_to_zeroes, DQS_zeros_to_ones);
Expand Down Expand Up @@ -251,13 +251,13 @@ TEST_F(DDR4_WindowStats_Tests, Pattern_2) {
// DQs bus
// For write and read the number of clock cycles the strobes stay on is
// (("number of reads/writes" * "size in bits") / bus_size) / bus_rate
int number_of_cycles = ((2 * SZ_BITS(rd_data)) / 8) / spec->dataRate;
uint64_t number_of_cycles = ((2 * SZ_BITS(rd_data)) / 8) / spec->dataRate;

// Only read
int DQS_ones = number_of_cycles * spec->dataRate;
int DQS_zeros = DQS_ones;
int DQS_zeros_to_ones = DQS_ones;
int DQS_ones_to_zeros = DQS_zeros;
uint64_t DQS_ones = number_of_cycles * spec->dataRate;
uint64_t DQS_zeros = DQS_ones;
uint64_t DQS_zeros_to_ones = DQS_ones;
uint64_t DQS_ones_to_zeros = DQS_zeros;
EXPECT_EQ(stats.readDQSStats.ones, DQS_ones);
EXPECT_EQ(stats.readDQSStats.zeroes, DQS_zeros);
EXPECT_EQ(stats.readDQSStats.ones_to_zeroes, DQS_zeros_to_ones);
Expand Down Expand Up @@ -309,13 +309,13 @@ TEST_F(DDR4_WindowStats_Tests, Pattern_3) {
// DQs bus
// For write and read the number of clock cycles the strobes stay on is
// (("number of writes/reads" * "size in bits") / bus_size) / bus_rate
int number_of_cycles = ((2 * SZ_BITS(wr_data)) / 8) / spec->dataRate;
uint64_t number_of_cycles = ((2 * SZ_BITS(wr_data)) / 8) / spec->dataRate;

// Only writes
int DQS_ones = number_of_cycles * spec->dataRate;
int DQS_zeros = DQS_ones;
int DQS_zeros_to_ones = DQS_ones;
int DQS_ones_to_zeros = DQS_zeros;
uint64_t DQS_ones = number_of_cycles * spec->dataRate;
uint64_t DQS_zeros = DQS_ones;
uint64_t DQS_zeros_to_ones = DQS_ones;
uint64_t DQS_ones_to_zeros = DQS_zeros;
EXPECT_EQ(stats.writeDQSStats.ones, DQS_ones);
EXPECT_EQ(stats.writeDQSStats.zeroes, DQS_zeros);
EXPECT_EQ(stats.writeDQSStats.ones_to_zeroes, DQS_zeros_to_ones);
Expand Down Expand Up @@ -367,13 +367,13 @@ TEST_F(DDR4_WindowStats_Tests, Pattern_4) {
// DQs bus
// For write and read the number of clock cycles the strobes stay on is
// (("number of writes/reads" * "size in bits") / bus_size) / bus_rate
int number_of_cycles = ((2 * SZ_BITS(wr_data)) / 8) / spec->dataRate;
uint64_t number_of_cycles = ((2 * SZ_BITS(wr_data)) / 8) / spec->dataRate;

// Only reads
int DQS_ones = number_of_cycles * spec->dataRate;
int DQS_zeros = DQS_ones;
int DQS_zeros_to_ones = DQS_ones;
int DQS_ones_to_zeros = DQS_zeros;
uint64_t DQS_ones = number_of_cycles * spec->dataRate;
uint64_t DQS_zeros = DQS_ones;
uint64_t DQS_zeros_to_ones = DQS_ones;
uint64_t DQS_ones_to_zeros = DQS_zeros;
EXPECT_EQ(stats.readDQSStats.ones, DQS_ones);
EXPECT_EQ(stats.readDQSStats.zeroes, DQS_zeros);
EXPECT_EQ(stats.readDQSStats.ones_to_zeroes, DQS_zeros_to_ones);
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10 changes: 5 additions & 5 deletions tests/tests_drampower/interface/test_interface_ddr5.cpp
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Expand Up @@ -110,14 +110,14 @@ TEST_F(DDR5_WindowStats_Tests, Pattern_0) {

// For write and read the number of clock cycles the strobes stay on is
// currently ("size in bits" / bus_size) / bus_rate
int number_of_cycles = (SZ_BITS(wr_data) / 16) / spec->dataRate;
uint64_t number_of_cycles = (SZ_BITS(wr_data) / 16) / spec->dataRate;

// In this example read data and write data are the same size, so stats should be the same
uint_fast8_t dqspairs = 2 ? spec->bitWidth == 16 : 1;
int DQS_ones = dqspairs * number_of_cycles * spec->dataRate * 2; // Differential_Pairs * cycles * datarate * 2(Differential Pair)
int DQS_zeros = DQS_ones;
int DQS_zeros_to_ones = DQS_ones;
int DQS_ones_to_zeros = DQS_zeros;
uint64_t DQS_ones = dqspairs * number_of_cycles * spec->dataRate * 2; // Differential_Pairs * cycles * datarate * 2(Differential Pair)
uint64_t DQS_zeros = DQS_ones;
uint64_t DQS_zeros_to_ones = DQS_ones;
uint64_t DQS_ones_to_zeros = DQS_zeros;
EXPECT_EQ(stats.writeDQSStats.ones, DQS_ones);
EXPECT_EQ(stats.writeDQSStats.zeroes, DQS_zeros);
EXPECT_EQ(stats.writeDQSStats.ones_to_zeroes, DQS_zeros_to_ones);
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20 changes: 10 additions & 10 deletions tests/tests_drampower/interface/test_interface_lpddr5.cpp
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Expand Up @@ -137,12 +137,12 @@ TEST_F(LPDDR5_WindowStats_Tests, Pattern_0) {

// For read the number of clock cycles the strobes stay on is
// currently ("size in bits" / bus_size) / bus_rate
int number_of_cycles = (SZ_BITS(wr_data) / 16) / spec->dataRate;
uint64_t number_of_cycles = (SZ_BITS(wr_data) / 16) / spec->dataRate;

int DQS_ones = number_of_cycles * spec->dataRate;
int DQS_zeros = DQS_ones;
int DQS_zeros_to_ones = DQS_ones;
int DQS_ones_to_zeros = DQS_zeros;
uint64_t DQS_ones = number_of_cycles * spec->dataRate;
uint64_t DQS_zeros = DQS_ones;
uint64_t DQS_zeros_to_ones = DQS_ones;
uint64_t DQS_ones_to_zeros = DQS_zeros;

EXPECT_EQ(stats.readDQSStats.ones, DQS_ones);
EXPECT_EQ(stats.readDQSStats.zeroes, DQS_zeros);
Expand Down Expand Up @@ -309,12 +309,12 @@ TEST_F(LPDDR5_WindowStats_Tests, Pattern_3_BG_Mode) {
EXPECT_EQ(stats.commandBus.ones_to_zeroes, 21);
EXPECT_EQ(stats.commandBus.zeroes_to_ones, 21);

int number_of_cycles = (SZ_BITS(wr_data) / 16) / spec->dataRate;
uint64_t number_of_cycles = (SZ_BITS(wr_data) / 16) / spec->dataRate;

int DQS_ones = number_of_cycles * spec->dataRate;
int DQS_zeros = DQS_ones;
int DQS_zeros_to_ones = DQS_ones;
int DQS_ones_to_zeros = DQS_zeros;
uint64_t DQS_ones = number_of_cycles * spec->dataRate;
uint64_t DQS_zeros = DQS_ones;
uint64_t DQS_zeros_to_ones = DQS_ones;
uint64_t DQS_ones_to_zeros = DQS_zeros;

EXPECT_EQ(stats.readDQSStats.ones, DQS_ones);
EXPECT_EQ(stats.readDQSStats.zeroes, DQS_zeros);
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4 changes: 2 additions & 2 deletions tests/tests_misc/test_bus_extended.cpp
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Expand Up @@ -128,7 +128,7 @@ TEST_F(ExtendedBusIdlePatternTest, Load_Width_64)

auto expected = util::Bus::burst_t();

auto pattern_gen = [] (size_t i) -> uint8_t {
auto pattern_gen = [] (size_t i) -> size_t {
return i;
};

Expand Down Expand Up @@ -161,7 +161,7 @@ TEST_F(ExtendedBusIdlePatternTest, Load_Width_512)

auto expected = util::Bus::burst_t();

auto pattern_gen = [] (size_t i) -> uint8_t {
auto pattern_gen = [] (size_t i) -> size_t {
return i;
};

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